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authorIngo Molnar <mingo@kernel.org>2016-06-14 12:25:07 +0200
committerIngo Molnar <mingo@kernel.org>2016-06-14 12:25:07 +0200
commitf6f4bbc997ed23540d23ff3f073dd1ac091c6984 (patch)
tree9148c4c99607822abc0a58c80d658a6e85990c8b /arch/x86/kernel/cpu
parentdb06d759d6cf903aeda8c107fd3abd366dd80200 (diff)
parentce53da02ebfbe93ec58dd6150b28b4606330ead5 (diff)
downloadlinux-f6f4bbc997ed23540d23ff3f073dd1ac091c6984.tar.bz2
Merge branch 'x86/cpu' into x86/platform, to avoid conflict
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/cpu')
-rw-r--r--arch/x86/kernel/cpu/intel.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 6e2ffbebbcdb..c1a89bc026ac 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -300,15 +300,14 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
}
/*
- * P4 Xeon errata 037 workaround.
+ * P4 Xeon erratum 037 workaround.
* Hardware prefetcher may cause stale data to be loaded into the cache.
*/
if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
if (msr_set_bit(MSR_IA32_MISC_ENABLE,
- MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
- > 0) {
+ MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
pr_info("CPU: C0 stepping P4 Xeon detected.\n");
- pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
+ pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
}
}