diff options
| author | Tony Luck <tony.luck@intel.com> | 2020-09-29 19:13:13 -0700 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2020-09-30 07:49:58 +0200 |
| commit | ed9705e4ad1c19ae51ed0cb4c112f9eb6dfc69fc (patch) | |
| tree | e01340865df7e7bbdf386f600596979f8cdd2ecc /arch/x86/kernel/cpu | |
| parent | fd258dc4442c5c1c069c6b5b42bfe7d10cddda95 (diff) | |
| download | linux-ed9705e4ad1c19ae51ed0cb4c112f9eb6dfc69fc.tar.bz2 | |
x86/mce: Drop AMD-specific "DEFERRED" case from Intel severity rule list
Way back in v3.19 Intel and AMD shared the same machine check severity
grading code. So it made sense to add a case for AMD DEFERRED errors in
commit
e3480271f592 ("x86, mce, severity: Extend the the mce_severity mechanism to handle UCNA/DEFERRED error")
But later in v4.2 AMD switched to a separate grading function in
commit
bf80bbd7dcf5 ("x86/mce: Add an AMD severities-grading function")
Belatedly drop the DEFERRED case from the Intel rule list.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200930021313.31810-3-tony.luck@intel.com
Diffstat (limited to 'arch/x86/kernel/cpu')
| -rw-r--r-- | arch/x86/kernel/cpu/mce/severity.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/severity.c index 567ce09a0286..e0722461bb57 100644 --- a/arch/x86/kernel/cpu/mce/severity.c +++ b/arch/x86/kernel/cpu/mce/severity.c @@ -97,10 +97,6 @@ static struct severity { EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0) ), MCESEV( - DEFERRED, "Deferred error", - NOSER, MASK(MCI_STATUS_UC|MCI_STATUS_DEFERRED|MCI_STATUS_POISON, MCI_STATUS_DEFERRED) - ), - MCESEV( KEEP, "Corrected error", NOSER, BITCLR(MCI_STATUS_UC) ), |