diff options
| author | Mike Travis <mike.travis@hpe.com> | 2022-04-06 14:51:48 -0500 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2022-04-07 17:24:39 +0200 |
| commit | bb3ab81bdbd53f88f26ffabc9fb15bd8466486ec (patch) | |
| tree | 3534ad1cb685b43d75f0afdb4b9e0bbdcec6f596 /arch/x86/kernel/apic | |
| parent | d812f7c475c6a4dcfff02a85fbfd7a9c87e6a094 (diff) | |
| download | linux-bb3ab81bdbd53f88f26ffabc9fb15bd8466486ec.tar.bz2 | |
x86/platform/uv: Update TSC sync state for UV5
The UV5 platform synchronizes the TSCs among all chassis, and will not
proceed to OS boot without achieving synchronization. Previous UV
platforms provided a register indicating successful synchronization.
This is no longer available on UV5. On this platform TSC_ADJUST
should not be reset by the kernel.
Signed-off-by: Mike Travis <mike.travis@hpe.com>
Signed-off-by: Steve Wahl <steve.wahl@hpe.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20220406195149.228164-3-steve.wahl@hpe.com
Diffstat (limited to 'arch/x86/kernel/apic')
| -rw-r--r-- | arch/x86/kernel/apic/x2apic_uv_x.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index f5a48e66e4f5..a6e9c2794ef5 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -199,7 +199,13 @@ static void __init uv_tsc_check_sync(void) int mmr_shift; char *state; - /* Different returns from different UV BIOS versions */ + /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */ + if (!is_uv(UV2|UV3|UV4)) { + mark_tsc_async_resets("UV5+"); + return; + } + + /* UV2,3,4, UV BIOS TSC sync state available */ mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); mmr_shift = is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; |