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| author | Arthur Chunqi Li <yzt356@gmail.com> | 2013-09-16 16:11:44 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2013-10-10 18:22:54 +0200 |
| commit | 7854cbca815562a49d50bbc6f31599312853d1f4 (patch) | |
| tree | 514f0a7a9e0bb345a371a4288d0ab2318cb4a7a3 /arch/x86/include/uapi/asm/msr-index.h | |
| parent | 8a3c1a33476f6bfebd07954e2277dbc88003bd37 (diff) | |
| download | linux-7854cbca815562a49d50bbc6f31599312853d1f4.tar.bz2 | |
KVM: nVMX: Fully support nested VMX preemption timer
This patch contains the following two changes:
1. Fix the bug in nested preemption timer support. If vmexit L2->L0
with some reasons not emulated by L1, preemption timer value should
be save in such exits.
2. Add support of "Save VMX-preemption timer value" VM-Exit controls
to nVMX.
With this patch, nested VMX preemption timer features are fully
supported.
Signed-off-by: Arthur Chunqi Li <yzt356@gmail.com>
Reviewed-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/include/uapi/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/uapi/asm/msr-index.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index bb0465090ae5..b93e09a0fa21 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -536,6 +536,7 @@ /* MSR_IA32_VMX_MISC bits */ #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) +#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F /* AMD-V MSRs */ #define MSR_VM_CR 0xc0010114 |