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authorIngo Molnar <mingo@elte.hu>2009-07-03 08:29:25 -0500
committerThomas Gleixner <tglx@linutronix.de>2010-02-16 17:19:11 +0100
commit17c0e7107bed3d578864e6519f7f4e4c324c8f58 (patch)
tree966cff3219781d2ef1ac66988d26207f771e0bf2 /arch/x86/include/asm/atomic.h
parent3bef444797f7624f8fbd27f4e0334ce96a108725 (diff)
downloadlinux-17c0e7107bed3d578864e6519f7f4e4c324c8f58.tar.bz2
x86: Mark atomic irq ops raw for 32bit legacy
The atomic ops emulation for 32bit legacy CPUs floods the tracer with irq off/on entries. The irq disabled regions are short and therefor not interesting when chasing long irq disabled latencies. Mark them raw and keep them out of the trace. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/include/asm/atomic.h')
-rw-r--r--arch/x86/include/asm/atomic.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h
index 8baaa719fa7f..8f8217b9bdac 100644
--- a/arch/x86/include/asm/atomic.h
+++ b/arch/x86/include/asm/atomic.h
@@ -187,10 +187,10 @@ static inline int atomic_add_return(int i, atomic_t *v)
#ifdef CONFIG_M386
no_xadd: /* Legacy 386 processor */
- local_irq_save(flags);
+ raw_local_irq_save(flags);
__i = atomic_read(v);
atomic_set(v, i + __i);
- local_irq_restore(flags);
+ raw_local_irq_restore(flags);
return i + __i;
#endif
}