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| author | Kan Liang <kan.liang@linux.intel.com> | 2021-08-26 08:32:43 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2021-08-31 13:59:37 +0200 |
| commit | 4034fb207e302cc0b1f304084d379640c1fb1436 (patch) | |
| tree | 5cdc7438263a5e1ccd1a7945414421999a12f8bb /arch/x86/events | |
| parent | f01d7d558e1855d4aa8e927b86111846536dd476 (diff) | |
| download | linux-4034fb207e302cc0b1f304084d379640c1fb1436.tar.bz2 | |
perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints
SPR M3UPI have the exact same event constraints as ICX, so add the
constraints.
Fixes: 2a8e51eae7c8 ("perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-8-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events')
| -rw-r--r-- | arch/x86/events/intel/uncore_snbep.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index cd53057fd52d..eb2c6cea9d0d 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5776,6 +5776,7 @@ static struct intel_uncore_type spr_uncore_upi = { static struct intel_uncore_type spr_uncore_m3upi = { SPR_UNCORE_PCI_COMMON_FORMAT(), .name = "m3upi", + .constraints = icx_uncore_m3upi_constraints, }; static struct intel_uncore_type spr_uncore_mdf = { |