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| author | Kan Liang <Kan.liang@intel.com> | 2017-09-08 17:34:48 -0400 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2017-09-25 09:36:17 +0200 |
| commit | 1aaccc40a1864053da26605b0297be16dd52641e (patch) | |
| tree | f9611311989f8dfd59233db64a191cdb9e724592 /arch/x86/events | |
| parent | b09c146f8f63c0e03adba74df76bf9c2be466fec (diff) | |
| download | linux-1aaccc40a1864053da26605b0297be16dd52641e.tar.bz2 | |
perf/x86/msr: Add missing CPU IDs
Goldmont, Glodmont plus and Xeon Phi have MSR_SMI_COUNT as well.
Signed-off-by: Kan Liang <Kan.liang@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: ak@linux.intel.com
Cc: peterz@infradead.org
Cc: piotr.luc@intel.com
Cc: harry.pan@intel.com
Cc: srinivas.pandruvada@linux.intel.com
Link: http://lkml.kernel.org/r/20170908213449.6224-2-kan.liang@intel.com
Diffstat (limited to 'arch/x86/events')
| -rw-r--r-- | arch/x86/events/msr.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 4bb3ec69e8ea..06723671ae4e 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -63,6 +63,14 @@ static bool test_intel(int idx) case INTEL_FAM6_ATOM_SILVERMONT1: case INTEL_FAM6_ATOM_SILVERMONT2: case INTEL_FAM6_ATOM_AIRMONT: + + case INTEL_FAM6_ATOM_GOLDMONT: + case INTEL_FAM6_ATOM_DENVERTON: + + case INTEL_FAM6_ATOM_GEMINI_LAKE: + + case INTEL_FAM6_XEON_PHI_KNL: + case INTEL_FAM6_XEON_PHI_KNM: if (idx == PERF_MSR_SMI) return true; break; |