summaryrefslogtreecommitdiffstats
path: root/arch/x86/events/core.c
diff options
context:
space:
mode:
authorPu Wen <puwen@hygon.cn>2018-09-23 17:34:47 +0800
committerBorislav Petkov <bp@suse.de>2018-09-27 18:28:57 +0200
commit6d0ef316b9f8ea03fa867debda70b2f11a0b9736 (patch)
treefedc78b52d0dd05ba9183c9c83ece2216d408aec /arch/x86/events/core.c
parent0b13bec787dccca96f8c431da732657ae01baf9a (diff)
downloadlinux-6d0ef316b9f8ea03fa867debda70b2f11a0b9736.tar.bz2
x86/events: Add Hygon Dhyana support to PMU infrastructure
The PMU architecture for the Hygon Dhyana CPU is similar to the AMD Family 17h one. To support it, call amd_pmu_init() to share the AMD PMU initialization flow, and change the PMU name to "HYGON". The Hygon Dhyana CPU supports both legacy and extension PMC MSRs (perf counter registers and event selection registers), so add Hygon Dhyana support in the similar way as AMD does. Signed-off-by: Pu Wen <puwen@hygon.cn> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: tglx@linutronix.de Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: x86@kernel.org Cc: thomas.lendacky@amd.com Link: https://lkml.kernel.org/r/9d93ed54a975f33ef7247e0967960f4ce5d3d990.1537533369.git.puwen@hygon.cn
Diffstat (limited to 'arch/x86/events/core.c')
-rw-r--r--arch/x86/events/core.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index dfb2f7c0d019..9c562f5fbde0 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1776,6 +1776,10 @@ static int __init init_hw_perf_events(void)
case X86_VENDOR_AMD:
err = amd_pmu_init();
break;
+ case X86_VENDOR_HYGON:
+ err = amd_pmu_init();
+ x86_pmu.name = "HYGON";
+ break;
default:
err = -ENOTSUPP;
}