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| author | Ingo Molnar <mingo@kernel.org> | 2018-03-31 07:30:17 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2018-03-31 07:30:17 +0200 |
| commit | 169310f71fc820fe153ec04c6a111e444a68d6d5 (patch) | |
| tree | a586d0f08548159ceb8527ff59f8414579f70c1f /arch/x86/Kconfig.cpu | |
| parent | b3c39758c8a6972f02b43f83dba7fe7a352371b9 (diff) | |
| parent | c2a9838452a4d71f76103c18c926468a9ea05713 (diff) | |
| download | linux-169310f71fc820fe153ec04c6a111e444a68d6d5.tar.bz2 | |
Merge branch 'linus' into locking/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/Kconfig.cpu')
| -rw-r--r-- | arch/x86/Kconfig.cpu | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 8b8d2297d486..638411f22267 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -315,19 +315,6 @@ config X86_L1_CACHE_SHIFT default "4" if MELAN || M486 || MGEODEGX1 default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX -config X86_PPRO_FENCE - bool "PentiumPro memory ordering errata workaround" - depends on M686 || M586MMX || M586TSC || M586 || M486 || MGEODEGX1 - ---help--- - Old PentiumPro multiprocessor systems had errata that could cause - memory operations to violate the x86 ordering standard in rare cases. - Enabling this option will attempt to work around some (but not all) - occurrences of this problem, at the cost of much heavier spinlock and - memory barrier operations. - - If unsure, say n here. Even distro kernels should think twice before - enabling this: there are few systems, and an unlikely bug. - config X86_F00F_BUG def_bool y depends on M586MMX || M586TSC || M586 || M486 |