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authorOlof Johansson <olof@lixom.net>2013-01-16 19:58:08 -0800
committerOlof Johansson <olof@lixom.net>2013-01-16 19:58:58 -0800
commit5046e385b4426e229a6beb4bce480762af91a6fc (patch)
tree65b4bff2c913a18840b3c58892853d51b942ac43 /arch/tile/kernel/pci.c
parenta73b59c51ab288d81b515b504790267f594884b8 (diff)
parentb86dc0d8c12bbb9fed3f392c284bdc7114ce00c1 (diff)
downloadlinux-5046e385b4426e229a6beb4bce480762af91a6fc.tar.bz2
Merge branch 'v3.8-samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
From Kukjin Kim: That branch fixes build error for S3C24XX/S3C64xx. And corrects dw-mshc properties on EXYNOS5 DT and fixes IRQ mapping on Cragganmore board. * 'v3.8-samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: S3C64XX: Fix up IRQ mapping for balblair on Cragganmore ARM: dts: correct the dw-mshc timing properties as per binding ARM: S3C64XX: Fix build error with CONFIG_S3C_DEV_FB disabled + Linux 3.8-rc3 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/tile/kernel/pci.c')
-rw-r--r--arch/tile/kernel/pci.c23
1 files changed, 8 insertions, 15 deletions
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index aac1cd586966..67237d34c2e2 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -81,7 +81,7 @@ EXPORT_SYMBOL(pcibios_align_resource);
* controller_id is the controller number, config type is 0 or 1 for
* config0 or config1 operations.
*/
-static int __devinit tile_pcie_open(int controller_id, int config_type)
+static int tile_pcie_open(int controller_id, int config_type)
{
char filename[32];
int fd;
@@ -97,8 +97,7 @@ static int __devinit tile_pcie_open(int controller_id, int config_type)
/*
* Get the IRQ numbers from the HV and set up the handlers for them.
*/
-static int __devinit tile_init_irqs(int controller_id,
- struct pci_controller *controller)
+static int tile_init_irqs(int controller_id, struct pci_controller *controller)
{
char filename[32];
int fd;
@@ -237,7 +236,7 @@ static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
-static void __devinit fixup_read_and_payload_sizes(void)
+static void fixup_read_and_payload_sizes(void)
{
struct pci_dev *dev = NULL;
int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
@@ -379,7 +378,7 @@ subsys_initcall(pcibios_init);
/*
* No bus fixups needed.
*/
-void __devinit pcibios_fixup_bus(struct pci_bus *bus)
+void pcibios_fixup_bus(struct pci_bus *bus)
{
/* Nothing needs to be done. */
}
@@ -458,11 +457,8 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
* specified bus & slot.
*/
-static int __devinit tile_cfg_read(struct pci_bus *bus,
- unsigned int devfn,
- int offset,
- int size,
- u32 *val)
+static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
+ int size, u32 *val)
{
struct pci_controller *controller = bus->sysdata;
int busnum = bus->number & 0xff;
@@ -504,11 +500,8 @@ static int __devinit tile_cfg_read(struct pci_bus *bus,
* See tile_cfg_read() for relevant comments.
* Note that "val" is the value to write, not a pointer to that value.
*/
-static int __devinit tile_cfg_write(struct pci_bus *bus,
- unsigned int devfn,
- int offset,
- int size,
- u32 val)
+static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
+ int size, u32 val)
{
struct pci_controller *controller = bus->sysdata;
int busnum = bus->number & 0xff;