diff options
author | Chris Metcalf <cmetcalf@tilera.com> | 2010-06-25 16:41:11 -0400 |
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committer | Chris Metcalf <cmetcalf@tilera.com> | 2010-07-06 13:34:01 -0400 |
commit | fb702b942bf638baa6cbbbda9f76794db62921ef (patch) | |
tree | c065b0ab61cbb80b6209c725836a6864624b3c46 /arch/tile/include/asm/irq.h | |
parent | de5d9bf6541736dc7ad264d2b5cc99bc1b2ad958 (diff) | |
download | linux-fb702b942bf638baa6cbbbda9f76794db62921ef.tar.bz2 |
arch/tile: Enable more sophisticated IRQ model for 32-bit chips.
This model is based on the on-chip interrupt model used by the
TILE-Gx next-generation hardware, and interacts much more cleanly
with the Linux generic IRQ layer.
The change includes modifications to the Tilera hypervisor, which
are reflected in the hypervisor headers in arch/tile/include/arch/.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/tile/include/asm/irq.h')
-rw-r--r-- | arch/tile/include/asm/irq.h | 62 |
1 files changed, 56 insertions, 6 deletions
diff --git a/arch/tile/include/asm/irq.h b/arch/tile/include/asm/irq.h index 9be1f849fac9..572fd3ef1d73 100644 --- a/arch/tile/include/asm/irq.h +++ b/arch/tile/include/asm/irq.h @@ -23,15 +23,65 @@ /* IRQ numbers used for linux IPIs. */ #define IRQ_RESCHEDULE 1 -/* The HV interrupt state object. */ -DECLARE_PER_CPU(HV_IntrState, dev_intr_state); - void ack_bad_irq(unsigned int irq); /* - * Paravirtualized drivers should call this when their init calls - * discover a valid HV IRQ. + * Different ways of handling interrupts. Tile interrupts are always + * per-cpu; there is no global interrupt controller to implement + * enable/disable. Most onboard devices can send their interrupts to + * many tiles at the same time, and Tile-specific drivers know how to + * deal with this. + * + * However, generic devices (usually PCIE based, sometimes GPIO) + * expect that interrupts will fire on a single core at a time and + * that the irq can be enabled or disabled from any core at any time. + * We implement this by directing such interrupts to a single core. + * + * One added wrinkle is that PCI interrupts can be either + * hardware-cleared (legacy interrupts) or software cleared (MSI). + * Other generic device systems (GPIO) are always software-cleared. + * + * The enums below are used by drivers for onboard devices, including + * the internals of PCI root complex and GPIO. They allow the driver + * to tell the generic irq code what kind of interrupt is mapped to a + * particular IRQ number. + */ +enum { + /* per-cpu interrupt; use enable/disable_percpu_irq() to mask */ + TILE_IRQ_PERCPU, + /* global interrupt, hardware responsible for clearing. */ + TILE_IRQ_HW_CLEAR, + /* global interrupt, software responsible for clearing. */ + TILE_IRQ_SW_CLEAR, +}; + + +/* + * Paravirtualized drivers should call this when they dynamically + * allocate a new IRQ or discover an IRQ that was pre-allocated by the + * hypervisor for use with their particular device. This gives the + * IRQ subsystem an opportunity to do interrupt-type-specific + * initialization. + * + * ISSUE: We should modify this API so that registering anything + * except percpu interrupts also requires providing callback methods + * for enabling and disabling the interrupt. This would allow the + * generic IRQ code to proxy enable/disable_irq() calls back into the + * PCI subsystem, which in turn could enable or disable the interrupt + * at the PCI shim. */ -void tile_irq_activate(unsigned int irq); +void tile_irq_activate(unsigned int irq, int tile_irq_type); + +/* + * For onboard, non-PCI (e.g. TILE_IRQ_PERCPU) devices, drivers know + * how to use enable/disable_percpu_irq() to manage interrupts on each + * core. We can't use the generic enable/disable_irq() because they + * use a single reference count per irq, rather than per cpu per irq. + */ +void enable_percpu_irq(unsigned int irq); +void disable_percpu_irq(unsigned int irq); + + +void setup_irq_regs(void); #endif /* _ASM_TILE_IRQ_H */ |