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author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-06-16 09:46:24 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-06-16 09:46:24 -0700 |
commit | f8f44f09eaa2bfb40651e7fc6054d65c8091499a (patch) | |
tree | d68df2dca22c6450b1cbb43cd314a47557920187 /arch/sh/mm/cache-debugfs.c | |
parent | f49cc57cc9d1686bdca068c40bc43f1690aa02d3 (diff) | |
parent | 261a9af671a79b750cb170bac620601d686535c1 (diff) | |
download | linux-f8f44f09eaa2bfb40651e7fc6054d65c8091499a.tar.bz2 |
Merge branch 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x
* 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x:
sh: sh7724: Add USBHS DMAEngine support
sh: ecovec: Add renesas_usbhs support
sh, exec: remove redundant set_fs(USER_DS)
drivers: sh: resume enabled clocks fix
dmaengine: shdma: SH_DMAC_MAX_CHANNELS message fix
sh: Fix up xchg/cmpxchg corruption with gUSA RB.
sh: Remove compressed kernel libgcc dependency.
sh: fix wrong icache/dcache address-array start addr in cache-debugfs.
Diffstat (limited to 'arch/sh/mm/cache-debugfs.c')
-rw-r--r-- | arch/sh/mm/cache-debugfs.c | 25 |
1 files changed, 5 insertions, 20 deletions
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c index 52411462c409..115725198038 100644 --- a/arch/sh/mm/cache-debugfs.c +++ b/arch/sh/mm/cache-debugfs.c @@ -26,9 +26,9 @@ static int cache_seq_show(struct seq_file *file, void *iter) { unsigned int cache_type = (unsigned int)file->private; struct cache_info *cache; - unsigned int waysize, way, cache_size; - unsigned long ccr, base; - static unsigned long addrstart = 0; + unsigned int waysize, way; + unsigned long ccr; + unsigned long addrstart = 0; /* * Go uncached immediately so we don't skew the results any @@ -45,28 +45,13 @@ static int cache_seq_show(struct seq_file *file, void *iter) } if (cache_type == CACHE_TYPE_DCACHE) { - base = CACHE_OC_ADDRESS_ARRAY; + addrstart = CACHE_OC_ADDRESS_ARRAY; cache = ¤t_cpu_data.dcache; } else { - base = CACHE_IC_ADDRESS_ARRAY; + addrstart = CACHE_IC_ADDRESS_ARRAY; cache = ¤t_cpu_data.icache; } - /* - * Due to the amount of data written out (depending on the cache size), - * we may be iterated over multiple times. In this case, keep track of - * the entry position in addrstart, and rewind it when we've hit the - * end of the cache. - * - * Likewise, the same code is used for multiple caches, so care must - * be taken for bouncing addrstart back and forth so the appropriate - * cache is hit. - */ - cache_size = cache->ways * cache->sets * cache->linesz; - if (((addrstart & 0xff000000) != base) || - (addrstart & 0x00ffffff) > cache_size) - addrstart = base; - waysize = cache->sets; /* |