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| author | ShihPo Hung <shihpo.hung@sifive.com> | 2019-06-18 17:39:15 +0800 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2019-06-26 15:10:30 -0700 |
| commit | 0db7f5cd4aeba4cc63d0068598b3350eba8bb4cd (patch) | |
| tree | f8e41ececf51961446756ab84ee9f4cc41ee1df4 /arch/riscv | |
| parent | e3f9dada0abe1864bf467e84d201144eddb9ef88 (diff) | |
| download | linux-0db7f5cd4aeba4cc63d0068598b3350eba8bb4cd.tar.bz2 | |
riscv: mm: Fix code comment
Fix the comment since vmalloc_fault doesn't reach
flush_tlb_fix_spurious_fault.
Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: linux-riscv@lists.infradead.org
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/mm/fault.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index 3e2708c626a8..f960c3f4ce47 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -272,9 +272,6 @@ vmalloc_fault: * entries, but in RISC-V, SFENCE.VMA specifies an * ordering constraint, not a cache flush; it is * necessary even after writing invalid entries. - * Relying on flush_tlb_fix_spurious_fault would - * suffice, but the extra traps reduce - * performance. So, eagerly SFENCE.VMA. */ local_flush_tlb_page(addr); |