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| author | Zong Li <zong.li@sifive.com> | 2020-01-02 11:09:54 +0800 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2020-01-03 00:47:02 -0800 |
| commit | 0da310e82d3a9bff6ef6b0f2fbf45d1a05cc64fe (patch) | |
| tree | f8e5eeb96d120146213c3421f7f05b65b67f8dd2 /arch/riscv | |
| parent | ac51e005fe1456a288929a41d71adc6224e912d2 (diff) | |
| download | linux-0da310e82d3a9bff6ef6b0f2fbf45d1a05cc64fe.tar.bz2 | |
riscv: gcov: enable gcov for RISC-V
This patch enables GCOV code coverage measurement on RISC-V.
Lightly tested on QEMU and Hifive Unleashed board, seems to work as
expected.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Jonathan Corbet <corbet@lwn.net>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d8efbaa78d67..a31169b02ec0 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -64,6 +64,7 @@ config RISCV select SPARSEMEM_STATIC if 32BIT select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU select HAVE_ARCH_MMAP_RND_BITS if MMU + select ARCH_HAS_GCOV_PROFILE_ALL config ARCH_MMAP_RND_BITS_MIN default 18 if 64BIT |