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authorAtish Patra <atish.patra@wdc.com>2019-10-08 18:06:37 -0700
committerJonathan Corbet <corbet@lwn.net>2019-12-19 09:32:45 -0700
commit1d5c17e470286b8211e8a18d0f85ae89dec4e8d8 (patch)
treef8f03e5a2b3cca199352c3cfa3fa44a4d7062bd6 /arch/riscv
parenteb43135117adc88ba3fd8b15a649c4bceff79962 (diff)
downloadlinux-1d5c17e470286b8211e8a18d0f85ae89dec4e8d8.tar.bz2
RISC-V: Typo fixes in image header and documentation.
There are some typos in boot image header and riscv boot documentation. Fix the typos. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Link: https://lore.kernel.org/r/20191009010637.9955-1-atish.patra@wdc.com Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/include/asm/image.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/include/asm/image.h b/arch/riscv/include/asm/image.h
index 7b0f92ba0acc..e0b319af3681 100644
--- a/arch/riscv/include/asm/image.h
+++ b/arch/riscv/include/asm/image.h
@@ -42,7 +42,7 @@
* @res2: reserved
* @magic: Magic number (RISC-V specific; deprecated)
* @magic2: Magic number 2 (to match the ARM64 'magic' field pos)
- * @res4: reserved (will be used for PE COFF offset)
+ * @res3: reserved (will be used for PE COFF offset)
*
* The intention is for this header format to be shared between multiple
* architectures to avoid a proliferation of image header formats.
@@ -59,7 +59,7 @@ struct riscv_image_header {
u64 res2;
u64 magic;
u32 magic2;
- u32 res4;
+ u32 res3;
};
#endif /* __ASSEMBLY__ */
#endif /* _ASM_RISCV_IMAGE_H */