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| author | Christoffer Dall <christoffer.dall@arm.com> | 2019-12-12 20:50:55 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-01-19 16:05:10 +0000 |
| commit | b6ae256afd32f96bec0117175b329d0dd617655e (patch) | |
| tree | 1bc03d09b49e89f9b00e8664bc9cb19eb3ac6bff /arch/riscv/net | |
| parent | fd6988496e79a6a4bdb514a4655d2920209eb85d (diff) | |
| download | linux-b6ae256afd32f96bec0117175b329d0dd617655e.tar.bz2 | |
KVM: arm64: Only sign-extend MMIO up to register width
On AArch64 you can do a sign-extended load to either a 32-bit or 64-bit
register, and we should only sign extend the register up to the width of
the register as specified in the operation (by using the 32-bit Wn or
64-bit Xn register specifier).
As it turns out, the architecture provides this decoding information in
the SF ("Sixty-Four" -- how cute...) bit.
Let's take advantage of this with the usual 32-bit/64-bit header file
dance and do the right thing on AArch64 hosts.
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20191212195055.5541-1-christoffer.dall@arm.com
Diffstat (limited to 'arch/riscv/net')
0 files changed, 0 insertions, 0 deletions