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| author | Andrea Parri <parri.andrea@gmail.com> | 2018-02-20 11:17:28 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-02-26 08:44:50 -0800 |
| commit | ab4af60534107c55b00fa462eca0385dcef92384 (patch) | |
| tree | 5a2242af17a08f037469be77cf33ed49e9aeb4b4 /arch/riscv/include | |
| parent | 4a3928c6f8a53fa1aed28ccba227742486e8ddcb (diff) | |
| download | linux-ab4af60534107c55b00fa462eca0385dcef92384.tar.bz2 | |
riscv/barrier: Define __smp_{mb,rmb,wmb}
Introduce __smp_{mb,rmb,wmb}, and rely on the generic definitions
for smp_{mb,rmb,wmb}. A first consequence is that smp_{mb,rmb,wmb}
map to a compiler barrier on !SMP (while their definition remains
unchanged on SMP). As a further consequence, smp_load_acquire and
smp_store_release have "fence rw,rw" instead of "fence iorw,iorw".
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/barrier.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index c0319cbf1eec..5510366d169a 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -34,9 +34,9 @@ #define wmb() RISCV_FENCE(ow,ow) /* These barriers do not need to enforce ordering on devices, just memory. */ -#define smp_mb() RISCV_FENCE(rw,rw) -#define smp_rmb() RISCV_FENCE(r,r) -#define smp_wmb() RISCV_FENCE(w,w) +#define __smp_mb() RISCV_FENCE(rw,rw) +#define __smp_rmb() RISCV_FENCE(r,r) +#define __smp_wmb() RISCV_FENCE(w,w) /* * This is a very specific barrier: it's currently only used in two places in |