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authorLinus Torvalds <torvalds@linux-foundation.org>2019-03-07 12:52:36 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2019-03-07 12:52:36 -0800
commitd72cb8c7d9dbd9ce820c80f3fddb56b296ba96fc (patch)
tree0a5c1fce60589ead0a9fb719ddbbdf8daef83bca /arch/riscv/include
parentbe37f21a08ce65c7632c7f45e1755a4b07f278a0 (diff)
parent13fd5de06514458eb320188b7a815d65696efd99 (diff)
downloadlinux-d72cb8c7d9dbd9ce820c80f3fddb56b296ba96fc.tar.bz2
Merge tag 'riscv-for-linus-5.1-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux
Pull RISC-V updates from Palmer Dabbelt: "This contains the vast majority of the RISC-V patches for this merge window. It includes: - A handful of cleanups to our kernel prints, most of which are things I should have caught the first time. - We now provide an HWCAP that contains the ISA extensions that all enabled processors support, as supposed to just looking at the first enabled processor. - We no longer spin forever waiting for all harts to boot. - A fixmap implementation, which is coupled to some cleanups in our MM code. The only outstanding patches I know of right now are Vincent Chen's patches to fix c.ebreak handling in the kernel, the v2 of which was posted this morning. I'd like those in the MW, but I didn't want to hold up everything else. The patch set is based on top of my last fixes submission, but I've tested it with a conflict-free merge from v5.0. I'm doing this rather than my "just go rebase everything" flow due to a discussion with Linus, but if I misunderstood then just let me know and I'll do something else. It's also the first time I've taken a PR into my own tree, so let me know if I screwed that one up. I've used my standard testing flow (QEMU in Fedora), but now that we're starting to get the kernel in better shape I think it's time to impose some more testing here -- specifically I'm going to require that patches boot on the HiFive Unleashed because we're getting to the point where we can actually expect that to work. I haven't done that for this tag, but I'm going to do it for future ones. I know the board is a bit expensive and not everyone has one, but if I've sent you a free one and your patches break the boot then I'm going to yell at you :). If you don't have one then please indicate how you tested in your cover letter, and if you have a board then please add your Tested-by to patches if they work for your testing flow" * tag 'riscv-for-linus-5.1-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: arch: riscv: fix logic error in parse_dtb RISC-V: Assign hwcap as per comman capabilities. RISC-V: Compare cpuid with NR_CPUS before mapping. RISC-V: Allow hartid-to-cpuid function to fail. RISC-V: Remove NR_CPUs check during hartid search from DT RISC-V: Move cpuid to hartid mapping to SMP. RISC-V: Do not wait indefinitely in __cpu_up RISC-V: Free-up initrd in free_initrd_mem() RISC-V: Implement compile-time fixed mappings RISC-V: Move setup_vm() to mm/init.c RISC-V: Move setup_bootmem() to mm/init.c RISC-V: Setup init_mm before parse_early_param() riscv: remove the HAVE_KPROBES option riscv: use for_each_of_cpu_node iterator riscv: treat cpu devicetree nodes without status as enabled riscv: fix riscv_of_processor_hartid() comment riscv: use pr_info and friends riscv: add missing newlines to printk messages
Diffstat (limited to 'arch/riscv/include')
-rw-r--r--arch/riscv/include/asm/fixmap.h44
-rw-r--r--arch/riscv/include/asm/pgtable.h1
-rw-r--r--arch/riscv/include/asm/smp.h18
3 files changed, 58 insertions, 5 deletions
diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h
new file mode 100644
index 000000000000..57afe604b495
--- /dev/null
+++ b/arch/riscv/include/asm/fixmap.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
+ */
+
+#ifndef _ASM_RISCV_FIXMAP_H
+#define _ASM_RISCV_FIXMAP_H
+
+#include <linux/kernel.h>
+#include <linux/sizes.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+/*
+ * Here we define all the compile-time 'special' virtual addresses.
+ * The point is to have a constant address at compile time, but to
+ * set the physical address only in the boot process.
+ *
+ * These 'compile-time allocated' memory buffers are page-sized. Use
+ * set_fixmap(idx,phys) to associate physical memory with fixmap indices.
+ */
+enum fixed_addresses {
+ FIX_HOLE,
+ FIX_EARLYCON_MEM_BASE,
+ __end_of_fixed_addresses
+};
+
+#define FIXADDR_SIZE (__end_of_fixed_addresses * PAGE_SIZE)
+#define FIXADDR_TOP (PAGE_OFFSET)
+#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
+
+#define FIXMAP_PAGE_IO PAGE_KERNEL
+
+#define __early_set_fixmap __set_fixmap
+
+#define __late_set_fixmap __set_fixmap
+#define __late_clear_fixmap(idx) __set_fixmap((idx), 0, FIXMAP_PAGE_CLEAR)
+
+extern void __set_fixmap(enum fixed_addresses idx,
+ phys_addr_t phys, pgprot_t prot);
+
+#include <asm-generic/fixmap.h>
+
+#endif /* _ASM_RISCV_FIXMAP_H */
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index a8179a8c1491..1141364d990e 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -404,6 +404,7 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
#define kern_addr_valid(addr) (1) /* FIXME */
#endif
+extern void setup_bootmem(void);
extern void paging_init(void);
static inline void pgtable_cache_init(void)
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 41aa73b476f4..636a934f013a 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -19,16 +19,17 @@
#include <linux/thread_info.h>
#define INVALID_HARTID ULONG_MAX
+
+struct seq_file;
+extern unsigned long boot_cpu_hartid;
+
+#ifdef CONFIG_SMP
/*
* Mapping between linux logical cpu index and hartid.
*/
extern unsigned long __cpuid_to_hartid_map[NR_CPUS];
#define cpuid_to_hartid_map(cpu) __cpuid_to_hartid_map[cpu]
-struct seq_file;
-
-#ifdef CONFIG_SMP
-
/* print IPI stats */
void show_ipi_stats(struct seq_file *p, int prec);
@@ -58,7 +59,14 @@ static inline void show_ipi_stats(struct seq_file *p, int prec)
static inline int riscv_hartid_to_cpuid(int hartid)
{
- return 0;
+ if (hartid == boot_cpu_hartid)
+ return 0;
+
+ return -1;
+}
+static inline unsigned long cpuid_to_hartid_map(int cpu)
+{
+ return boot_cpu_hartid;
}
static inline void riscv_cpuid_to_hartid_mask(const struct cpumask *in,