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| author | Paul Mackerras <paulus@samba.org> | 2006-01-15 17:30:44 +1100 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-01-15 17:30:44 +1100 |
| commit | a7fdd90bc43e3e9cb08bc1b13650024d419b89e5 (patch) | |
| tree | 5c99a41b9d157186668ed63c001f72a09965143b /arch/ppc/kernel/misc.S | |
| parent | e8625d463560198cff7cb3eb22886c47d728d501 (diff) | |
| download | linux-a7fdd90bc43e3e9cb08bc1b13650024d419b89e5.tar.bz2 | |
[PATCH] ppc: Remove powermac support from ARCH=ppc
This makes it possible to build kernels for PReP and/or CHRP
with ARCH=ppc by removing the (non-building) powermac support.
It's now also possible to select PReP and CHRP independently.
Powermac users should now build with ARCH=powerpc instead of
ARCH=ppc. (This does mean that it is no longer possible to
build a 32-bit kernel for a G5.)
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/kernel/misc.S')
| -rw-r--r-- | arch/ppc/kernel/misc.S | 72 |
1 files changed, 0 insertions, 72 deletions
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S index fb5658bba285..c3427eed8345 100644 --- a/arch/ppc/kernel/misc.S +++ b/arch/ppc/kernel/misc.S @@ -204,78 +204,6 @@ _GLOBAL(call_setup_cpu) mtctr r5 bctr -#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx) - -/* This gets called by via-pmu.c to switch the PLL selection - * on 750fx CPU. This function should really be moved to some - * other place (as most of the cpufreq code in via-pmu - */ -_GLOBAL(low_choose_750fx_pll) - /* Clear MSR:EE */ - mfmsr r7 - rlwinm r0,r7,0,17,15 - mtmsr r0 - - /* If switching to PLL1, disable HID0:BTIC */ - cmplwi cr0,r3,0 - beq 1f - mfspr r5,SPRN_HID0 - rlwinm r5,r5,0,27,25 - sync - mtspr SPRN_HID0,r5 - isync - sync - -1: - /* Calc new HID1 value */ - mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */ - rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */ - rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */ - or r4,r4,r5 - mtspr SPRN_HID1,r4 - - /* Store new HID1 image */ - rlwinm r6,r1,0,0,18 - lwz r6,TI_CPU(r6) - slwi r6,r6,2 - addis r6,r6,nap_save_hid1@ha - stw r4,nap_save_hid1@l(r6) - - /* If switching to PLL0, enable HID0:BTIC */ - cmplwi cr0,r3,0 - bne 1f - mfspr r5,SPRN_HID0 - ori r5,r5,HID0_BTIC - sync - mtspr SPRN_HID0,r5 - isync - sync - -1: - /* Return */ - mtmsr r7 - blr - -_GLOBAL(low_choose_7447a_dfs) - /* Clear MSR:EE */ - mfmsr r7 - rlwinm r0,r7,0,17,15 - mtmsr r0 - - /* Calc new HID1 value */ - mfspr r4,SPRN_HID1 - insrwi r4,r3,1,9 /* insert parameter into bit 9 */ - sync - mtspr SPRN_HID1,r4 - sync - isync - - /* Return */ - mtmsr r7 - blr - -#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */ - /* * complement mask on the msr then "or" some values on. * _nmask_and_or_msr(nmask, value_to_or) |