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| author | Anton Vorontsov <avorontsov@ru.mvista.com> | 2010-02-18 16:57:27 +0300 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-03-04 10:42:58 -0600 |
| commit | 6f3d395a5c77e6ccddd59a5221e1354b22c29531 (patch) | |
| tree | 2ead51a96e1f72f3df04069143f8a228e947b73f /arch/powerpc | |
| parent | 43a5a01bcc5b53c67878f043b4a1b31eaa87a360 (diff) | |
| download | linux-6f3d395a5c77e6ccddd59a5221e1354b22c29531.tar.bz2 | |
powerpc/86xx: Convert gef_pic_lock to raw_spinlock
Interrupt controllers' hooks are executed in the atomic context, so
they are not permitted to sleep (with RT kernels non-raw spinlocks are
sleepable). So, gef_pic_lock has to be a real (non-sleepable) spinlock.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/platforms/86xx/gef_pic.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c index 0110a8736d33..7ad9c0df7707 100644 --- a/arch/powerpc/platforms/86xx/gef_pic.c +++ b/arch/powerpc/platforms/86xx/gef_pic.c @@ -49,7 +49,7 @@ #define gef_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) -static DEFINE_SPINLOCK(gef_pic_lock); +static DEFINE_RAW_SPINLOCK(gef_pic_lock); static void __iomem *gef_pic_irq_reg_base; static struct irq_host *gef_pic_irq_host; @@ -118,11 +118,11 @@ static void gef_pic_mask(unsigned int virq) hwirq = gef_irq_to_hw(virq); - spin_lock_irqsave(&gef_pic_lock, flags); + raw_spin_lock_irqsave(&gef_pic_lock, flags); mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); mask &= ~(1 << hwirq); out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask); - spin_unlock_irqrestore(&gef_pic_lock, flags); + raw_spin_unlock_irqrestore(&gef_pic_lock, flags); } static void gef_pic_mask_ack(unsigned int virq) @@ -141,11 +141,11 @@ static void gef_pic_unmask(unsigned int virq) hwirq = gef_irq_to_hw(virq); - spin_lock_irqsave(&gef_pic_lock, flags); + raw_spin_lock_irqsave(&gef_pic_lock, flags); mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); mask |= (1 << hwirq); out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask); - spin_unlock_irqrestore(&gef_pic_lock, flags); + raw_spin_unlock_irqrestore(&gef_pic_lock, flags); } static struct irq_chip gef_pic_chip = { @@ -199,7 +199,7 @@ void __init gef_pic_init(struct device_node *np) /* Map the devices registers into memory */ gef_pic_irq_reg_base = of_iomap(np, 0); - spin_lock_irqsave(&gef_pic_lock, flags); + raw_spin_lock_irqsave(&gef_pic_lock, flags); /* Initialise everything as masked. */ out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_INTR_MASK, 0); @@ -208,7 +208,7 @@ void __init gef_pic_init(struct device_node *np) out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_MCP_MASK, 0); out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_MCP_MASK, 0); - spin_unlock_irqrestore(&gef_pic_lock, flags); + raw_spin_unlock_irqrestore(&gef_pic_lock, flags); /* Map controller */ gef_pic_cascade_irq = irq_of_parse_and_map(np, 0); |