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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2007-03-10 00:05:37 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@klappe.arndb.de> | 2007-03-10 00:07:50 +0100 |
| commit | 94b2a4393c500a620de90c3266d595926302e26b (patch) | |
| tree | cde58177f430751b67a7aa47f3f89042e91357bf /arch/powerpc/mm/hash_utils_64.c | |
| parent | 50b520d4efbce45281f58112789470ec7965fd33 (diff) | |
| download | linux-94b2a4393c500a620de90c3266d595926302e26b.tar.bz2 | |
[POWERPC] Fix spu SLB invalidations
The SPU code doesn't properly invalidate SPUs SLBs when necessary,
for example when changing a segment size from the hugetlbfs code. In
addition, it saves and restores the SLB content on context switches
which makes it harder to properly handle those invalidations.
This patch removes the saving & restoring for now, something more
efficient might be found later on. It also adds a spu_flush_all_slbs(mm)
that can be used by the core mm code to flush the SLBs of all SPEs that
are running a given mm at the time of the flush.
In order to do that, it adds a spinlock to the list of all SPEs and move
some bits & pieces from spufs to spu_base.c
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm/hash_utils_64.c')
| -rw-r--r-- | arch/powerpc/mm/hash_utils_64.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index c0d2a694fa30..3c7fe2c65b5a 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -685,6 +685,9 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap) "non-cacheable mapping\n"); psize = mmu_vmalloc_psize = MMU_PAGE_4K; } +#ifdef CONFIG_SPE_BASE + spu_flush_all_slbs(mm); +#endif } if (user_region) { if (psize != get_paca()->context.user_psize) { @@ -759,6 +762,9 @@ void hash_preload(struct mm_struct *mm, unsigned long ea, mmu_psize_defs[MMU_PAGE_4K].sllp; get_paca()->context = mm->context; slb_flush_and_rebolt(); +#ifdef CONFIG_SPE_BASE + spu_flush_all_slbs(mm); +#endif } } if (mm->context.user_psize == MMU_PAGE_64K) |