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| author | Nicholas Piggin <npiggin@gmail.com> | 2018-04-01 15:38:13 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2018-04-03 22:14:27 +1000 |
| commit | a2b5e056b75ee6ef0777817644a456b36b96ce38 (patch) | |
| tree | 02711ff4c5dc10a6ab6cb756c4bbbc5d1720e2e8 /arch/powerpc/kernel/idle_book3s.S | |
| parent | b6f534d1a642a9b6263fd52df30806171fbc331e (diff) | |
| download | linux-a2b5e056b75ee6ef0777817644a456b36b96ce38.tar.bz2 | |
powerpc/powernv: Fix SMT4 forcing idle code
The PSSCR value is not stored to PACA_REQ_PSSCR if the CPU does not
have the XER[SO] bug.
Fix this by storing up-front, outside the workaround code. The initial
test is not required because it is a slow path.
The workaround is made to depend on CONFIG_KVM_BOOK3S_HV_POSSIBLE, to
match pnv_power9_force_smt4_catch() where it is used. Drop the comment
on pnv_power9_force_smt4_catch() as it's no longer true.
Fixes: 7672691a08c8 ("powerpc/powernv: Provide a way to force a core into SMT4 mode")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel/idle_book3s.S')
| -rw-r--r-- | arch/powerpc/kernel/idle_book3s.S | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S index 903ec2a5c76c..81defb6a9b74 100644 --- a/arch/powerpc/kernel/idle_book3s.S +++ b/arch/powerpc/kernel/idle_book3s.S @@ -442,20 +442,20 @@ _GLOBAL(power9_offline_stop) * r3 contains desired PSSCR register value. */ _GLOBAL(power9_idle_stop) -BEGIN_FTR_SECTION - lwz r5, PACA_DONT_STOP(r13) - cmpwi r5, 0 - bne 1f std r3, PACA_REQ_PSSCR(r13) +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE +BEGIN_FTR_SECTION sync lwz r5, PACA_DONT_STOP(r13) cmpwi r5, 0 bne 1f END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG) +#endif mtspr SPRN_PSSCR,r3 LOAD_REG_ADDR(r4,power_enter_stop) b pnv_powersave_common /* No return */ +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 1: /* * We get here when TM / thread reconfiguration bug workaround @@ -465,6 +465,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG) li r3, 0 std r3, PACA_REQ_PSSCR(r13) blr /* return 0 for wakeup cause / SRR1 value */ +#endif /* * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1, |