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authorMihai Caraman <mihai.caraman@freescale.com>2012-08-06 03:27:07 +0000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-09-05 15:35:52 +1000
commit8b64a9dfb091f1eca8b7e58da82f1e7d1d5fe0ad (patch)
tree9d0bfd7ecd07c02fef68e7b198a0560340bf0846 /arch/powerpc/include/asm/exception-64e.h
parent79b5c8dbaa4528a6fd03a4d9d8a6d56a46293a3a (diff)
downloadlinux-8b64a9dfb091f1eca8b7e58da82f1e7d1d5fe0ad.tar.bz2
powerpc/booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests. Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest SPRG4-7 registers will be clobbered. For bolted TLB miss exception handlers, which is the version currently supported by KVM, use SPRN_SPRG_GEN_SCRATCH aka SPRG0 instead of SPRN_SPRG_TLB_SCRATCH aka SPRG6. Keep using TLB PACA slots to fit in one 64-byte cache line. For critical exception handlers use SPRG3 instead of SPRG7. Provide a routine to store and restore user-visible SPRGs. This will be subsequently used to restore VDSO information in SPRG3. Add EX_R13 to paca slots to free up SPRG3 and change the critical exception epilog to use it. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/exception-64e.h')
-rw-r--r--arch/powerpc/include/asm/exception-64e.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
index e73452f09019..51fa43e536b9 100644
--- a/arch/powerpc/include/asm/exception-64e.h
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -46,8 +46,9 @@
#define EX_CR (1 * 8)
#define EX_R10 (2 * 8)
#define EX_R11 (3 * 8)
-#define EX_R14 (4 * 8)
-#define EX_R15 (5 * 8)
+#define EX_R13 (4 * 8)
+#define EX_R14 (5 * 8)
+#define EX_R15 (6 * 8)
/*
* The TLB miss exception uses different slots.