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| author | Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> | 2020-07-01 12:52:31 +0530 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2020-07-16 13:00:22 +1000 |
| commit | d358042793183a57094dac45a44116e1165ac593 (patch) | |
| tree | ffe420d327ab58d413398b7277034de4f8a301ae /arch/powerpc/include/asm/cacheflush.h | |
| parent | 32db09d992ddc7d145595cff49cccfe14e018266 (diff) | |
| download | linux-d358042793183a57094dac45a44116e1165ac593.tar.bz2 | |
powerpc/pmem: Add flush routines using new pmem store and sync instruction
Start using dcbstps; phwsync; sequence for flushing persistent memory range.
The new instructions are implemented as a variant of dcbf and hwsync and on
P8 and P9 they will be executed as those instructions. We avoid using them on
older hardware. This helps to avoid difficult to debug bugs.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200701072235.223558-4-aneesh.kumar@linux.ibm.com
Diffstat (limited to 'arch/powerpc/include/asm/cacheflush.h')
| -rw-r--r-- | arch/powerpc/include/asm/cacheflush.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h index de600b915a3c..54764c6e922d 100644 --- a/arch/powerpc/include/asm/cacheflush.h +++ b/arch/powerpc/include/asm/cacheflush.h @@ -6,6 +6,7 @@ #include <linux/mm.h> #include <asm/cputable.h> +#include <asm/cpu_has_feature.h> #ifdef CONFIG_PPC_BOOK3S_64 /* |