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authorJon Loeliger <jdl@freescale.com>2008-01-25 16:36:47 -0600
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 08:45:37 -0600
commit762931571edcf4067bc8f0de929752eb424b039e (patch)
treeb58aa49dc8865107cd5b7227a204f1d73e525e4f /arch/powerpc/boot
parent6e050d4e35659d26f4ca4c63d47e606d8aea763d (diff)
downloadlinux-762931571edcf4067bc8f0de929752eb424b039e.tar.bz2
[POWERPC] Convert StorCenter DTS file to /dts-v1/ format.
Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/storcenter.dts73
1 files changed, 38 insertions, 35 deletions
diff --git a/arch/powerpc/boot/dts/storcenter.dts b/arch/powerpc/boot/dts/storcenter.dts
index 6aa1d695e644..2204874ac5f3 100644
--- a/arch/powerpc/boot/dts/storcenter.dts
+++ b/arch/powerpc/boot/dts/storcenter.dts
@@ -11,6 +11,8 @@
* warranty of any kind, whether express or implied.
*/
+/dts-v1/;
+
/ {
model = "StorCenter";
compatible = "storcenter";
@@ -30,19 +32,19 @@
PowerPC,8241@0 {
device_type = "cpu";
reg = <0>;
- clock-frequency = <d# 200000000>; /* Hz */
- timebase-frequency = <d# 25000000>; /* Hz */
+ clock-frequency = <200000000>;
+ timebase-frequency = <25000000>;
bus-frequency = <0>; /* from bootwrapper */
- i-cache-line-size = <d# 32>; /* bytes */
- d-cache-line-size = <d# 32>; /* bytes */
- i-cache-size = <4000>;
- d-cache-size = <4000>;
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <16384>;
+ d-cache-size = <16384>;
};
};
memory {
device_type = "memory";
- reg = <00000000 04000000>; /* 64MB @ 0x0 */
+ reg = <0x00000000 0x04000000>; /* 64MB @ 0x0 */
};
soc@fc000000 {
@@ -51,15 +53,15 @@
device_type = "soc";
compatible = "fsl,mpc8241", "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
- ranges = <0 fc000000 100000>;
- reg = <fc000000 100000>; /* EUMB */
+ ranges = <0x0 0xfc000000 0x100000>;
+ reg = <0xfc000000 0x100000>; /* EUMB */
bus-frequency = <0>; /* fixed by loader */
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
- reg = <3000 100>;
+ reg = <0x3000 0x100>;
interrupts = <5 2>;
interrupt-parent = <&mpic>;
@@ -73,9 +75,9 @@
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <4500 20>;
- clock-frequency = <d# 97553800>; /* Hz */
- current-speed = <d# 115200>;
+ reg = <0x4500 0x20>;
+ clock-frequency = <97553800>; /* Hz */
+ current-speed = <115200>;
interrupts = <9 2>;
interrupt-parent = <&mpic>;
};
@@ -84,10 +86,10 @@
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <4600 20>;
- clock-frequency = <d# 97553800>; /* Hz */
- current-speed = <d# 9600>;
- interrupts = <a 2>;
+ reg = <0x4600 0x20>;
+ clock-frequency = <97553800>; /* Hz */
+ current-speed = <9600>;
+ interrupts = <10 2>;
interrupt-parent = <&mpic>;
};
@@ -96,7 +98,7 @@
device_type = "open-pic";
compatible = "chrp,open-pic";
interrupt-controller;
- reg = <40000 40000>;
+ reg = <0x40000 0x40000>;
};
};
@@ -107,28 +109,29 @@
#interrupt-cells = <1>;
device_type = "pci";
compatible = "mpc10x-pci";
- reg = <fe800000 1000>;
- ranges = <01000000 0 0 fe000000 0 00c00000
- 02000000 0 80000000 80000000 0 70000000>;
- bus-range = <0 ff>;
- clock-frequency = <d# 97553800>; /* Hz */
+ reg = <0xfe800000 0x1000>;
+ ranges = <0x01000000 0x0 0x0 0xfe000000 0x0 0x00c00000
+ 0x02000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
+ bus-range = <0 0xff>;
+ clock-frequency = <97553800>;
interrupt-parent = <&mpic>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 13 - IDE */
- 6800 0 0 1 &mpic 0 1
- 6800 0 0 2 &mpic 0 1
- 6800 0 0 3 &mpic 0 1
+ 0x6800 0 0 1 &mpic 0 1
+ 0x6800 0 0 2 &mpic 0 1
+ 0x6800 0 0 3 &mpic 0 1
+ 0x6800 0 0 4 &mpic 0 1
/* IDSEL 14 - USB */
- 7000 0 0 1 &mpic 0 1
- 7000 0 0 2 &mpic 0 1
- 7000 0 0 3 &mpic 0 1
- 7000 0 0 4 &mpic 0 1
+ 0x7000 0 0 1 &mpic 0 1
+ 0x7000 0 0 2 &mpic 0 1
+ 0x7000 0 0 3 &mpic 0 1
+ 0x7000 0 0 4 &mpic 0 1
/* IDSEL 15 - ETH */
- 7800 0 0 1 &mpic 0 1
- 7800 0 0 2 &mpic 0 1
- 7800 0 0 3 &mpic 0 1
- 7800 0 0 4 &mpic 0 1
+ 0x7800 0 0 1 &mpic 0 1
+ 0x7800 0 0 2 &mpic 0 1
+ 0x7800 0 0 3 &mpic 0 1
+ 0x7800 0 0 4 &mpic 0 1
>;
};