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| author | John David Anglin <dave.anglin@bell.net> | 2015-10-14 20:32:11 -0400 |
|---|---|---|
| committer | Helge Deller <deller@gmx.de> | 2015-10-25 10:01:17 +0100 |
| commit | a01fece2e4185ac173abd16d10304d73d47ebf00 (patch) | |
| tree | ece0b00c66838ee95d2e83f92bf51b1a2b79a982 /arch/parisc | |
| parent | c59f419bdd1f056e1ceacbd29f7be7bcff746a5d (diff) | |
| download | linux-a01fece2e4185ac173abd16d10304d73d47ebf00.tar.bz2 | |
parisc: Change L1_CACHE_BYTES to 16
Change L1_CACHE_BYTES to 16 bytes.
Tested for 16 days on rp3440.
Additional remarks from Helge Deller:
Saves ~17 kb of kernel code/data and gives a slight performance improvement in
various test cases.
Signed-off-by: John David Anglin <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'arch/parisc')
| -rw-r--r-- | arch/parisc/include/asm/cache.h | 18 |
1 files changed, 5 insertions, 13 deletions
diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h index 47f11c707b65..3d0e17bcc8e9 100644 --- a/arch/parisc/include/asm/cache.h +++ b/arch/parisc/include/asm/cache.h @@ -7,20 +7,12 @@ /* - * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have - * 32-byte cachelines. The default configuration is not for SMP anyway, - * so if you're building for SMP, you should select the appropriate - * processor type. There is a potential livelock danger when running - * a machine with this value set too small, but it's more probable you'll - * just ruin performance. + * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors + * have 32-byte cachelines. The L1 length appears to be 16 bytes but this + * is not clearly documented. */ -#ifdef CONFIG_PA20 -#define L1_CACHE_BYTES 64 -#define L1_CACHE_SHIFT 6 -#else -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 -#endif +#define L1_CACHE_BYTES 16 +#define L1_CACHE_SHIFT 4 #ifndef __ASSEMBLY__ |