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authorWill Deacon <will.deacon@arm.com>2013-09-04 11:34:08 +0100
committerWill Deacon <will.deacon@arm.com>2014-10-20 18:49:18 +0100
commit2f083481cfd38320ebde0b83d836b967a2419d53 (patch)
treefc736d9067db7a55c448aced9a5630bdb1e85939 /arch/parisc
parent960a5597c39109ed2e12964cd9dc34857e5afee2 (diff)
downloadlinux-2f083481cfd38320ebde0b83d836b967a2419d53.tar.bz2
parisc: io: implement dummy relaxed accessor macros for writes
write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to parisc, in the same vein as the dummy definitions for the relaxed read accessors. Cc: Helge Deller <deller@gmx.de> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/parisc')
-rw-r--r--arch/parisc/include/asm/io.h12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/parisc/include/asm/io.h b/arch/parisc/include/asm/io.h
index 1f6d2ae7aba5..8cd0abf28ffb 100644
--- a/arch/parisc/include/asm/io.h
+++ b/arch/parisc/include/asm/io.h
@@ -217,10 +217,14 @@ static inline void writeq(unsigned long long q, volatile void __iomem *addr)
#define writel writel
#define writeq writeq
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
-#define readq_relaxed(addr) readq(addr)
+#define readb_relaxed(addr) readb(addr)
+#define readw_relaxed(addr) readw(addr)
+#define readl_relaxed(addr) readl(addr)
+#define readq_relaxed(addr) readq(addr)
+#define writeb_relaxed(b, addr) writeb(b, addr)
+#define writew_relaxed(w, addr) writew(w, addr)
+#define writel_relaxed(l, addr) writel(l, addr)
+#define writeq_relaxed(q, addr) writeq(q, addr)
#define mmiowb() do { } while (0)