diff options
| author | Nylon Chen <nylon7@andestech.com> | 2018-11-08 19:28:15 +0800 |
|---|---|---|
| committer | Greentime Hu <greentime@andestech.com> | 2018-11-22 18:13:51 +0800 |
| commit | e2f3f8b4a497d26bdcd55a53246ec2e613ae0fd4 (patch) | |
| tree | c6cbc184ba802977d2f2bfa44e238e697b4455ac /arch/nds32/kernel | |
| parent | a5234068e6dc18ae5300d678fbf3e129d9b93f78 (diff) | |
| download | linux-e2f3f8b4a497d26bdcd55a53246ec2e613ae0fd4.tar.bz2 | |
nds32: support hardware prefetcher
We add a config for user to enable or disable this feature.
It can be used to control the hardware prefetch function.
Signed-off-by: Nylon Chen <nylon7@andestech.com>
Acked-by: Greentime Hu <greentime@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
Diffstat (limited to 'arch/nds32/kernel')
| -rw-r--r-- | arch/nds32/kernel/head.S | 2 | ||||
| -rw-r--r-- | arch/nds32/kernel/setup.c | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/nds32/kernel/head.S b/arch/nds32/kernel/head.S index 2c8aac6201be..db64b78b1232 100644 --- a/arch/nds32/kernel/head.S +++ b/arch/nds32/kernel/head.S @@ -151,7 +151,7 @@ _tlb: #endif mtsr $r3, $TLB_MISC - mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp + mfsr $r0, $MISC_CTL ! Enable BTB, RTP, shadow sp, and HW_PRE ori $r0, $r0, #MISC_init mtsr $r0, $MISC_CTL diff --git a/arch/nds32/kernel/setup.c b/arch/nds32/kernel/setup.c index 4b774ca433a9..31d29d92478e 100644 --- a/arch/nds32/kernel/setup.c +++ b/arch/nds32/kernel/setup.c @@ -39,6 +39,7 @@ #define HWCAP_FPU_DP 0x040000 #define HWCAP_V2 0x080000 #define HWCAP_DX_REGS 0x100000 +#define HWCAP_HWPRE 0x200000 unsigned long cpu_id, cpu_rev, cpu_cfgid; bool has_fpu = false; @@ -75,6 +76,7 @@ static const char *hwcap_str[] = { "fpu_dp", "v2", "dx_regs", + "hw_pre", NULL, }; @@ -221,6 +223,11 @@ static void __init setup_cpuinfo(void) if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C) elf_hwcap |= HWCAP_L2C; +#ifdef CONFIG_HW_PRE + if (__nds32__mfsr(NDS32_SR_MISC_CTL) & MISC_CTL_makHWPRE_EN) + elf_hwcap |= HWCAP_HWPRE; +#endif + tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL); if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE)) tmp |= CACHE_CTL_mskDC_EN; |