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authorRalf Baechle <ralf@linux-mips.org>2014-05-21 11:42:10 +0200
committerRalf Baechle <ralf@linux-mips.org>2014-05-21 12:25:39 +0200
commite5eb925a1804c4a52994ba57f4f68ee7a9132905 (patch)
tree537ff44f413665231fd7932dfdce6d9c34661f0b /arch/mips
parent60b5f90d0fac7585f1a43ccdad06787b97eda0ab (diff)
downloadlinux-e5eb925a1804c4a52994ba57f4f68ee7a9132905.tar.bz2
MIPS: Change type of asid_cache to unsigned long
asid_cache must be unsigned long otherwise on 64 bit systems it will become 0 if the value in get_new_mmu_context() reaches 0xffffffff and in the end the assumption of ASID_FIRST_VERSION is not true anymore thus leads to more dangerous things. Initial patch by Yong Zhang <yong.zhang@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: libin <huawei.libin@huawei.com>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/include/asm/cpu-info.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index dc2135be2a3a..ff2707ab3295 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -39,14 +39,14 @@ struct cache_desc {
#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
struct cpuinfo_mips {
- unsigned int udelay_val;
- unsigned int asid_cache;
+ unsigned long asid_cache;
/*
* Capability and feature descriptor structure for MIPS CPU
*/
unsigned long options;
unsigned long ases;
+ unsigned int udelay_val;
unsigned int processor_id;
unsigned int fpu_id;
unsigned int msa_id;