diff options
| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2020-01-13 18:15:00 +0800 |
|---|---|---|
| committer | Paul Burton <paulburton@kernel.org> | 2020-01-23 10:26:48 -0800 |
| commit | 51522217f65f1f937f421d9f417cf0e714ef3c02 (patch) | |
| tree | 29384efccae4de2d23e641f8d07ef16273acecae /arch/mips | |
| parent | ba9196d2e005a07dc616a044a57b47665efe133d (diff) | |
| download | linux-51522217f65f1f937f421d9f417cf0e714ef3c02.tar.bz2 | |
MIPS: Loongson64: Bump ISA level to MIPSR2
Despite early sample of Loongson-3A1000, the whole Loongson64 family have
implemented all the features required by MIPS64 Release2. Thus we decide to
bump the ISA option to R2.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: chenhc@lemote.com
Cc: paul.burton@mips.com
Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/Kconfig | 6 | ||||
| -rw-r--r-- | arch/mips/include/asm/hazards.h | 4 |
2 files changed, 6 insertions, 4 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 75fca0cee9a2..08b6f3413c01 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1436,10 +1436,14 @@ config CPU_LOONGSON64 bool "Loongson 64-bit CPU" depends on SYS_HAS_CPU_LOONGSON64 select ARCH_HAS_PHYS_TO_DMA + select CPU_MIPSR2 + select CPU_HAS_PREFETCH select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES select CPU_SUPPORTS_MSA + select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT + select CPU_MIPSR2_IRQ_VI select WEAK_ORDERING select WEAK_REORDERING_BEYOND_LLSC select MIPS_ASID_BITS_VARIABLE @@ -1457,8 +1461,6 @@ config CPU_LOONGSON64 config LOONGSON3_ENHANCEMENT bool "New Loongson-3 CPU Enhancements" default n - select CPU_MIPSR2 - select CPU_HAS_PREFETCH depends on CPU_LOONGSON64 help New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index a4f48b0f5541..a0b92205f933 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -23,7 +23,7 @@ * TLB hazards */ #if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \ - !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT) + !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64) /* * MIPSR2 defines ehb for hazard avoidance @@ -158,7 +158,7 @@ do { \ } while (0) #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ - defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \ + defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \ defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR) /* |