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| author | Huacai Chen <chenhc@lemote.com> | 2017-03-16 21:00:28 +0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-04-10 11:56:08 +0200 |
| commit | 17c99d9421695a0e0de18bf1e7091d859e20ec1d (patch) | |
| tree | b85ec6aa09ba082e12840be02bc2ea09fda28071 /arch/mips | |
| parent | 294d62743754f1fefefccccb09f8deec48f00969 (diff) | |
| download | linux-17c99d9421695a0e0de18bf1e7091d859e20ec1d.tar.bz2 | |
MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6
Some newer Loongson-3 have 64 bytes cache lines, so select
MIPS_L1_CACHE_SHIFT_6.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15755/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f4dd2c322d4b..2afb41c52ba0 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1374,6 +1374,7 @@ config CPU_LOONGSON3 select WEAK_ORDERING select WEAK_REORDERING_BEYOND_LLSC select MIPS_PGD_C0_CONTEXT + select MIPS_L1_CACHE_SHIFT_6 select GPIOLIB help The Loongson 3 processor implements the MIPS64R2 instruction |