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authorLinus Torvalds <torvalds@linux-foundation.org>2009-03-30 10:36:35 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2009-03-30 10:36:35 -0700
commit915db32ddbc967f023fbf7d7f01cca9e05606a9b (patch)
tree1634540805af363e1514d132d9140aa585f9cc9d /arch/mips/sni/a20r.c
parentebc8eca169be0283d5a7ab54c4411dd59cfb0f27 (diff)
parent91e8a30e90144bcd0fead02dc57976f304c3b3f7 (diff)
downloadlinux-915db32ddbc967f023fbf7d7f01cca9e05606a9b.tar.bz2
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (21 commits) MIPS: Alchemy: PB1200: use SMC91X platform data. MIPS: Alchemy: MIPS hazard workarounds are not required. MIPS: Alchemy: provide cpu feature overrides. MIPS: Alchemy: unify CPU model constants. MIPS: Make a needlessly global symbol static in arch/mips/kernel/smp.c MIPS: Fix global namespace pollution in arch/mips/kernel/smp-up.c MIPS: Malta: make a needlessly global integer variable static MIPS: Use BUG_ON() where possible. MIPS: Convert obsolete irq_desc_t to struct irq_desc MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms MIPS: EMMA2RH: Set UART mapbase MIPS: EMMA2RH: Use set_irq_chip_and_handler_name MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO interrupts MIPS: Mark Eins: Fix cascading interrupt dispatcher MIPS: Au1000: convert to using gpiolib MIPS: Stop using <asm-generic/int-l64.h>. MIPS: Cavium: Add -Werror MIPS: Makefile: Add simple make install target. MIPS: Compat: Zero upper 32-bit of offset_high and offset_low. MIPS: __raw_spin_lock() may spin forever on ticket wrap. ...
Diffstat (limited to 'arch/mips/sni/a20r.c')
-rw-r--r--arch/mips/sni/a20r.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 3f8cf5eb2f06..7dd76fb3b645 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -219,7 +219,7 @@ void __init sni_a20r_irq_init(void)
int i;
for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
- set_irq_chip(i, &a20r_irq_type);
+ set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
sni_hwint = a20r_hwint;
change_c0_status(ST0_IM, IE_IRQ0);
setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);