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authorJohn Crispin <blogic@openwrt.org>2013-04-14 09:55:29 +0200
committerRalf Baechle <ralf@linux-mips.org>2013-05-08 01:19:12 +0200
commit51e396078412ef91f222b9834f09308746ac7049 (patch)
tree1dd877360061d64510a6d3c3808b6059ec42bd3b /arch/mips/ralink
parentfe98f612a1ef5a7ca0ecd26530509ce129838995 (diff)
downloadlinux-51e396078412ef91f222b9834f09308746ac7049.tar.bz2
MIPS: ralink: add memory definition for MT7620
Populate struct soc_info with the data that describes our RAM window. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5183/
Diffstat (limited to 'arch/mips/ralink')
-rw-r--r--arch/mips/ralink/mt7620.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index af19ae740162..0018b1a661f6 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
+
+ switch (dram_type) {
+ case SYSCFG0_DRAM_TYPE_SDRAM:
+ soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
+ soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
+ break;
+
+ case SYSCFG0_DRAM_TYPE_DDR1:
+ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
+ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
+ break;
+
+ case SYSCFG0_DRAM_TYPE_DDR2:
+ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
+ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
+ break;
+ default:
+ BUG();
+ }
+ soc_info->mem_base = MT7620_DRAM_BASE;
}