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| author | Christoph Hellwig <hch@lst.de> | 2018-08-04 10:23:16 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-08-13 08:31:31 -0700 |
| commit | 6ea0f26a7913b2a72f9cbe84e77ad2cbeaaa9dde (patch) | |
| tree | dc077f5075634c43587aa2658247e37b4004e59d /arch/mips/pci/pci-ip32.c | |
| parent | bec2e6ac353d5c8a47c6eea639136bac3990093e (diff) | |
| download | linux-6ea0f26a7913b2a72f9cbe84e77ad2cbeaaa9dde.tar.bz2 | |
RISC-V: implement low-level interrupt handling
Add support for a routine that dispatches exceptions with the interrupt
flags set to either the IPI or irqdomain code (and the clock source in the
future).
Loosely based on the irq-riscv-int.c irqchip driver from the RISC-V tree.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/mips/pci/pci-ip32.c')
0 files changed, 0 insertions, 0 deletions