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| author | David Daney <ddaney@caviumnetworks.com> | 2010-10-07 16:03:53 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-10-29 19:08:43 +0100 |
| commit | c9941158fd8a539a56b0e8a4740ec1f6beb23ea3 (patch) | |
| tree | 73e3868737061e1d5b0b61c182ea443e3ccd94e3 /arch/mips/mm | |
| parent | 468ffde46d429fbd291b0ef43a06afe9c837629f (diff) | |
| download | linux-c9941158fd8a539a56b0e8a4740ec1f6beb23ea3.tar.bz2 | |
MIPS: Octeon: Apply CN63XXP1 errata workarounds.
The CN63XXP1 needs a couple of workarounds to ensure memory is not written
in unexpected ways.
All PREF with hints in the range 0-4,6-24 are replaced with PREF 28. We
pass a flag to the assembler to cover compiler generated code, and patch
uasm for the dynamically generated code.
The write buffer threshold is reduced to 4.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1672/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/uasm.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index d2647a4e012b..23afdebc8e5c 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -405,7 +405,6 @@ I_u1u2u3(_mfc0) I_u1u2u3(_mtc0) I_u2u1u3(_ori) I_u3u1u2(_or) -I_u2s3u1(_pref) I_0(_rfe) I_u2s3u1(_sc) I_u2s3u1(_scd) @@ -427,6 +426,25 @@ I_u1(_syscall); I_u1u2s3(_bbit0); I_u1u2s3(_bbit1); +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#include <asm/octeon/octeon.h> +void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b, + unsigned int c) +{ + if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5) + /* + * As per erratum Core-14449, replace prefetches 0-4, + * 6-24 with 'pref 28'. + */ + build_insn(buf, insn_pref, c, 28, b); + else + build_insn(buf, insn_pref, c, a, b); +} +UASM_EXPORT_SYMBOL(uasm_i_pref); +#else +I_u2s3u1(_pref) +#endif + /* Handle labels. */ void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) { |