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authorPaul Cercueil <paul@crapouillou.net>2019-05-08 00:43:56 +0200
committerPaul Burton <paul.burton@mips.com>2019-07-21 15:23:23 -0700
commit3b25b763116482596227225bea7c03fcde11c9ed (patch)
treee7b3aa5066de745879645e748f8e38c912f05443 /arch/mips/mm
parent7176b6ac18469f63b3aa1f6e2997776ad81273b4 (diff)
downloadlinux-3b25b763116482596227225bea7c03fcde11c9ed.tar.bz2
MIPS: Rename JZRISC to XBURST
The real name of the CPU present in the JZ line of SoCs from Ingenic is XBurst, not JZRISC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> [paul.burton@mips.com: Leave /proc/cpuinfo string as-is.] Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/sc-mips.c2
-rw-r--r--arch/mips/mm/tlbex.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 394673991bab..9385ddbd6e47 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -225,7 +225,7 @@ static inline int __init mips_sc_probe(void)
* According to config2 it would be 5-ways, but that is contradicted
* by all documentation.
*/
- if (current_cpu_type() == CPU_JZRISC &&
+ if (current_cpu_type() == CPU_XBURST &&
mips_machtype == MACH_INGENIC_JZ4770)
c->scache.ways = 4;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 144ceb0fba88..efffeae7f789 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -610,7 +610,7 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l,
tlbw(p);
break;
- case CPU_JZRISC:
+ case CPU_XBURST:
tlbw(p);
uasm_i_nop(p);
break;