diff options
| author | Mathieu Malaterre <malat@debian.org> | 2018-12-03 22:23:43 +0100 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2018-12-03 13:42:38 -0800 |
| commit | 69095e3900b22bc289ade04ac548ae6b9e8f45ec (patch) | |
| tree | 2eb13009526bc88fc118b335db4bebf49e4fa078 /arch/mips/mm | |
| parent | 1aeba347b3a90a8b22f1c3eed0dcfba38bb8dbb8 (diff) | |
| download | linux-69095e3900b22bc289ade04ac548ae6b9e8f45ec.tar.bz2 | |
mips: annotate implicit fall throughs
There is a plan to build the kernel with -Wimplicit-fallthrough and
these places in the code produced warnings. Fix them up.
This patch produces no change in behaviour, but should be reviewed in
case these are actually bugs not intentional fallthoughs.
Signed-off-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Kees Cook <keescook@google.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 2 | ||||
| -rw-r--r-- | arch/mips/mm/tlbex.c | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 96d666a0f4a0..d0b64df51eb2 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1280,6 +1280,7 @@ static void probe_pcache(void) case CPU_VR4133: write_c0_config(config & ~VR41_CONF_P4K); + /* fall through */ case CPU_VR4131: /* Workaround for cache instruction bug of VR4131 */ if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || @@ -1527,6 +1528,7 @@ static void probe_pcache(void) c->dcache.flags |= MIPS_CACHE_PINDEX; break; } + /* fall through */ default: if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) c->dcache.flags |= MIPS_CACHE_ALIASES; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 067714291643..37b1cb246332 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -576,6 +576,7 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_R5500: if (m4kc_tlbp_war()) uasm_i_nop(p); + /* fall through */ case CPU_ALCHEMY: tlbw(p); break; |