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authorHuacai Chen <chenhc@lemote.com>2020-05-23 15:51:45 +0800
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-05-24 09:24:49 +0200
commit8267e78f020a8de2752754c42ec1d56e92431477 (patch)
tree022412532fa0a8ae7f4e8e481696bfd32922c5bb /arch/mips/mm
parent41528ba6afe62d472a729b223f8542ccc1156df1 (diff)
downloadlinux-8267e78f020a8de2752754c42ec1d56e92431477.tar.bz2
MIPS: Tidy up CP0.Config6 bits definition
CP0.Config6 is a Vendor-defined register whose bits definitions are different from one to another. Recently, Xuerui's Loongson-3 patch and Serge's P5600 patch make the definitions inconsistency and unclear. To make life easy, this patch tidy the definition up: 1, Add a _MTI_ infix for proAptiv/P5600 feature bits; 2, Add a _LOONGSON_ infix for Loongson-3 feature bits; 3, Add bit6/bit7 definition for Loongson-3 which will be used later. All existing users of these macros are updated. Cc: WANG Xuerui <git@xen0n.name> Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/c-r4k.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a9f55bf90967..6fb83ac7c475 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1073,12 +1073,12 @@ static inline int alias_74k_erratum(struct cpuinfo_mips *c)
if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
present = 1;
if (rev == PRID_REV_ENCODE_332(2, 4, 0))
- write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+ write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);
break;
case PRID_IMP_1074K:
if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
present = 1;
- write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+ write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);
}
break;
default: