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author | Mauro Carvalho Chehab <m.chehab@samsung.com> | 2014-05-21 23:03:15 -0300 |
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committer | Mauro Carvalho Chehab <m.chehab@samsung.com> | 2014-05-21 23:03:15 -0300 |
commit | e899966f626f1f657a4a7bac736c0b9ae5a243ea (patch) | |
tree | a4bb8362d871da67b41fee27bb85ad0bc83e0591 /arch/mips/mm | |
parent | ba0d342ecc21fbbe2f6c178f4479944d1fb34f3b (diff) | |
parent | 4b660a7f5c8099d88d1a43d8ae138965112592c7 (diff) | |
download | linux-e899966f626f1f657a4a7bac736c0b9ae5a243ea.tar.bz2 |
Merge tag 'v3.15-rc6' into patchwork
Linux 3.15-rc6
* tag 'v3.15-rc6': (1314 commits)
Linux 3.15-rc6
Btrfs: send, fix incorrect ref access when using extrefs
Btrfs: fix EIO on reading file after ioctl clone works on it
scripts/checksyscalls.sh: Make renameat optional
asm-generic: Add renameat2 syscall
ia64: add renameat2 syscall
parisc: add renameat2 syscall
m68k: add renameat2 syscall
sysfs: make sure read buffer is zeroed
ahci: imx: PLL clock needs 100us to settle down
PCI: Wrong register used to check pending traffic
target: fix memory leak on XCOPY
random: fix BUG_ON caused by accounting simplification
clk: tegra: Fix wrong value written to PLLE_AUX
staging: rtl8723au: Do not reset wdev->iftype in netdev_close()
ACPI / video: Revert native brightness quirk for ThinkPad T530
staging: rtl8723au: Use correct pipe type for USB interrupts
crush: decode and initialize chooseleaf_vary_r
libceph: fix corruption when using page_count 0 page in rbd
arm64: fix pud_huge() for 2-level pagetables
...
Diffstat (limited to 'arch/mips/mm')
-rw-r--r-- | arch/mips/mm/cache.c | 4 | ||||
-rw-r--r-- | arch/mips/mm/tlb-funcs.S | 4 | ||||
-rw-r--r-- | arch/mips/mm/tlbex.c | 7 |
3 files changed, 9 insertions, 6 deletions
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index e422b38d3113..9e67cdea3c74 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -29,15 +29,15 @@ void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); void (*flush_icache_range)(unsigned long start, unsigned long end); +EXPORT_SYMBOL_GPL(flush_icache_range); void (*local_flush_icache_range)(unsigned long start, unsigned long end); void (*__flush_cache_vmap)(void); void (*__flush_cache_vunmap)(void); void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size); -void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size); - EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range); +void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size); /* MIPS specific cache operations */ void (*flush_cache_sigtramp)(unsigned long addr); diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S index 30a494db99c2..a5427c6e9757 100644 --- a/arch/mips/mm/tlb-funcs.S +++ b/arch/mips/mm/tlb-funcs.S @@ -16,8 +16,10 @@ #define FASTPATH_SIZE 128 +EXPORT(tlbmiss_handler_setup_pgd_start) LEAF(tlbmiss_handler_setup_pgd) - .space 16 * 4 +1: j 1b /* Dummy, will be replaced. */ + .space 64 END(tlbmiss_handler_setup_pgd) EXPORT(tlbmiss_handler_setup_pgd_end) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index ee88367ab3ad..f99ec587b151 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1422,16 +1422,17 @@ static void build_r4000_tlb_refill_handler(void) extern u32 handle_tlbl[], handle_tlbl_end[]; extern u32 handle_tlbs[], handle_tlbs_end[]; extern u32 handle_tlbm[], handle_tlbm_end[]; -extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[]; +extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[]; +extern u32 tlbmiss_handler_setup_pgd_end[]; static void build_setup_pgd(void) { const int a0 = 4; const int __maybe_unused a1 = 5; const int __maybe_unused a2 = 6; - u32 *p = tlbmiss_handler_setup_pgd; + u32 *p = tlbmiss_handler_setup_pgd_start; const int tlbmiss_handler_setup_pgd_size = - tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; + tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start; #ifndef CONFIG_MIPS_PGD_C0_CONTEXT long pgdc = (long)pgd_current; #endif |