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| author | Ricardo Mendoza <ricmm@gentoo.org> | 2010-07-19 04:59:59 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-08-05 13:26:06 +0100 |
| commit | 58a6d45193a4f5af9d55f243779ea485656e3a22 (patch) | |
| tree | 493f9cbd858c38754374a2b90e5d467e052628ec /arch/mips/mm/sc-rm7k.c | |
| parent | 65ab2826c4185fc949c3a720186bd09d75ea14a4 (diff) | |
| download | linux-58a6d45193a4f5af9d55f243779ea485656e3a22.tar.bz2 | |
MIPS: RM7000: Make use of cache_op() instead of inline asm
Small cleanup of the cache code to get rid of inline asm, in preparation
to give tertiary cache support.
Signed-off-by: Ricardo Mendoza <ricmm@gentoo.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1476/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/sc-rm7k.c')
| -rw-r--r-- | arch/mips/mm/sc-rm7k.c | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c index de69bfbf506e..53634398a56d 100644 --- a/arch/mips/mm/sc-rm7k.c +++ b/arch/mips/mm/sc-rm7k.c @@ -95,16 +95,8 @@ static __cpuinit void __rm7k_sc_enable(void) write_c0_taglo(0); write_c0_taghi(0); - for (i = 0; i < scache_size; i += sc_lsize) { - __asm__ __volatile__ ( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD)); - } + for (i = 0; i < scache_size; i += sc_lsize) + cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i)); } static __cpuinit void rm7k_sc_enable(void) |