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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2021-10-20 14:49:13 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2021-10-24 17:24:47 +0200
commit95b8a5e0111a47e5ef780c04cb6293be33d6ee0d (patch)
tree0c54fd731b6ba11ed813b9225b4484042e281c71 /arch/mips/kernel
parent626bfa03729959ea9917181fb3d8ffaa1594d02a (diff)
downloadlinux-95b8a5e0111a47e5ef780c04cb6293be33d6ee0d.tar.bz2
MIPS: Remove NETLOGIC support
No (active) developer owns this hardware, so let's remove Linux support. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/cpu-probe.c84
-rw-r--r--arch/mips/kernel/idle.c2
-rw-r--r--arch/mips/kernel/perf_event_mipsxx.c86
3 files changed, 0 insertions, 172 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 630fcb4cb30e..ac0e2cfc6d57 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1886,87 +1886,6 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
}
}
-static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
-{
- decode_configs(c);
-
- if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
- c->cputype = CPU_ALCHEMY;
- __cpu_name[cpu] = "Au1300";
- /* following stuff is not for Alchemy */
- return;
- }
-
- c->options = (MIPS_CPU_TLB |
- MIPS_CPU_4KEX |
- MIPS_CPU_COUNTER |
- MIPS_CPU_DIVEC |
- MIPS_CPU_WATCH |
- MIPS_CPU_EJTAG |
- MIPS_CPU_LLSC);
-
- switch (c->processor_id & PRID_IMP_MASK) {
- case PRID_IMP_NETLOGIC_XLP2XX:
- case PRID_IMP_NETLOGIC_XLP9XX:
- case PRID_IMP_NETLOGIC_XLP5XX:
- c->cputype = CPU_XLP;
- __cpu_name[cpu] = "Broadcom XLPII";
- break;
-
- case PRID_IMP_NETLOGIC_XLP8XX:
- case PRID_IMP_NETLOGIC_XLP3XX:
- c->cputype = CPU_XLP;
- __cpu_name[cpu] = "Netlogic XLP";
- break;
-
- case PRID_IMP_NETLOGIC_XLR732:
- case PRID_IMP_NETLOGIC_XLR716:
- case PRID_IMP_NETLOGIC_XLR532:
- case PRID_IMP_NETLOGIC_XLR308:
- case PRID_IMP_NETLOGIC_XLR532C:
- case PRID_IMP_NETLOGIC_XLR516C:
- case PRID_IMP_NETLOGIC_XLR508C:
- case PRID_IMP_NETLOGIC_XLR308C:
- c->cputype = CPU_XLR;
- __cpu_name[cpu] = "Netlogic XLR";
- break;
-
- case PRID_IMP_NETLOGIC_XLS608:
- case PRID_IMP_NETLOGIC_XLS408:
- case PRID_IMP_NETLOGIC_XLS404:
- case PRID_IMP_NETLOGIC_XLS208:
- case PRID_IMP_NETLOGIC_XLS204:
- case PRID_IMP_NETLOGIC_XLS108:
- case PRID_IMP_NETLOGIC_XLS104:
- case PRID_IMP_NETLOGIC_XLS616B:
- case PRID_IMP_NETLOGIC_XLS608B:
- case PRID_IMP_NETLOGIC_XLS416B:
- case PRID_IMP_NETLOGIC_XLS412B:
- case PRID_IMP_NETLOGIC_XLS408B:
- case PRID_IMP_NETLOGIC_XLS404B:
- c->cputype = CPU_XLR;
- __cpu_name[cpu] = "Netlogic XLS";
- break;
-
- default:
- pr_info("Unknown Netlogic chip id [%02x]!\n",
- c->processor_id);
- c->cputype = CPU_XLR;
- break;
- }
-
- if (c->cputype == CPU_XLP) {
- set_isa(c, MIPS_CPU_ISA_M64R2);
- c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
- /* This will be updated again after all threads are woken up */
- c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
- } else {
- set_isa(c, MIPS_CPU_ISA_M64R1);
- c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
- }
- c->kscratch_mask = 0xf;
-}
-
#ifdef CONFIG_64BIT
/* For use by uaccess.h */
u64 __ua_limit;
@@ -2031,9 +1950,6 @@ void cpu_probe(void)
case PRID_COMP_INGENIC_E1:
cpu_probe_ingenic(c, cpu);
break;
- case PRID_COMP_NETLOGIC:
- cpu_probe_netlogic(c, cpu);
- break;
}
BUG_ON(!__cpu_name[cpu]);
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 1aca3b4db904..c81b3a039470 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -175,8 +175,6 @@ void __init check_wait(void)
case CPU_CAVIUM_OCTEON3:
case CPU_XBURST:
case CPU_LOONGSON32:
- case CPU_XLR:
- case CPU_XLP:
cpu_wait = r4k_wait;
break;
case CPU_LOONGSON64:
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 22e22c2de1c9..1641d274fe37 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1002,15 +1002,6 @@ static const struct mips_perf_event bmips5000_event_map
[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
};
-static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
- [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
- [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */
- [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
- [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
- [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
-};
-
/* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */
static const struct mips_perf_event mipsxxcore_cache_map
[PERF_COUNT_HW_CACHE_MAX]
@@ -1477,63 +1468,6 @@ static const struct mips_perf_event octeon_cache_map
},
};
-static const struct mips_perf_event xlp_cache_map
- [PERF_COUNT_HW_CACHE_MAX]
- [PERF_COUNT_HW_CACHE_OP_MAX]
- [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-[C(L1D)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
- [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
- [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
- },
-},
-[C(L1I)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
- [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
- },
-},
-[C(LL)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
- [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
- [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
- },
-},
-[C(DTLB)] = {
- /*
- * Only general DTLB misses are counted use the same event for
- * read and write.
- */
- [C(OP_READ)] = {
- [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
- },
- [C(OP_WRITE)] = {
- [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
- },
-},
-[C(ITLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
- },
- [C(OP_WRITE)] = {
- [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
- },
-},
-[C(BPU)] = {
- [C(OP_READ)] = {
- [C(RESULT_MISS)] = { 0x25, CNTR_ALL },
- },
-},
-};
-
static int __hw_perf_event_init(struct perf_event *event)
{
struct perf_event_attr *attr = &event->attr;
@@ -1953,20 +1887,6 @@ static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
return &raw_event;
}
-static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config)
-{
- unsigned int raw_id = config & 0xff;
-
- /* Only 1-63 are defined */
- if ((raw_id < 0x01) || (raw_id > 0x3f))
- return ERR_PTR(-EOPNOTSUPP);
-
- raw_event.cntr_mask = CNTR_ALL;
- raw_event.event_id = raw_id;
-
- return &raw_event;
-}
-
static int __init
init_hw_perf_events(void)
{
@@ -2091,12 +2011,6 @@ init_hw_perf_events(void)
mipspmu.general_event_map = &bmips5000_event_map;
mipspmu.cache_event_map = &bmips5000_cache_map;
break;
- case CPU_XLP:
- mipspmu.name = "xlp";
- mipspmu.general_event_map = &xlp_event_map;
- mipspmu.cache_event_map = &xlp_cache_map;
- mipspmu.map_raw_event = xlp_pmu_map_raw_event;
- break;
default:
pr_cont("Either hardware does not support performance "
"counters, or not yet implemented.\n");