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author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 18:32:51 +0200 |
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committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 22:24:51 +0200 |
commit | 43df4eb2fc9511e09c66252c3fec4f8933a77c73 (patch) | |
tree | 372ef0796bbfdf94373ce22b0489f6a26c127be8 /arch/mips/include | |
parent | a7fbed988f31d3bf92415226fdf2ffd54606ad93 (diff) | |
download | linux-43df4eb2fc9511e09c66252c3fec4f8933a77c73.tar.bz2 |
MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS
SB1250 uart bug is related to PASS 2 workarounds. Use config
CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include')
-rw-r--r-- | arch/mips/include/asm/mach-cavium-octeon/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-generic/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ip22/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ip27/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ip28/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ip30/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ip32/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-malta/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-rc32434/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-rm/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-sibyte/war.h | 2 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-tx49xx/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/war.h | 7 |
13 files changed, 0 insertions, 20 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h index 9aa4ea5522a9..0a2bf6b7af94 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/war.h +++ b/arch/mips/include/asm/mach-cavium-octeon/war.h @@ -10,7 +10,6 @@ #define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \ OCTEON_IS_MODEL(OCTEON_CN6XXX) diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h index 4f25636661d5..6b7de91435e3 100644 --- a/arch/mips/include/asm/mach-generic/war.h +++ b/arch/mips/include/asm/mach-generic/war.h @@ -9,6 +9,5 @@ #define __ASM_MACH_GENERIC_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #endif /* __ASM_MACH_GENERIC_WAR_H */ diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h index 09169cfbf932..70de6a5008d3 100644 --- a/arch/mips/include/asm/mach-ip22/war.h +++ b/arch/mips/include/asm/mach-ip22/war.h @@ -9,6 +9,5 @@ #define __ASM_MIPS_MACH_IP22_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #endif /* __ASM_MIPS_MACH_IP22_WAR_H */ diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h index 1c81d5464235..5b01e8fe245f 100644 --- a/arch/mips/include/asm/mach-ip27/war.h +++ b/arch/mips/include/asm/mach-ip27/war.h @@ -9,6 +9,5 @@ #define __ASM_MIPS_MACH_IP27_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #endif /* __ASM_MIPS_MACH_IP27_WAR_H */ diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h index ff66adbaaae5..ba4267e2d34d 100644 --- a/arch/mips/include/asm/mach-ip28/war.h +++ b/arch/mips/include/asm/mach-ip28/war.h @@ -9,6 +9,5 @@ #define __ASM_MIPS_MACH_IP28_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #endif /* __ASM_MIPS_MACH_IP28_WAR_H */ diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h index b00469a39835..f404e22b7798 100644 --- a/arch/mips/include/asm/mach-ip30/war.h +++ b/arch/mips/include/asm/mach-ip30/war.h @@ -6,6 +6,5 @@ #define __ASM_MIPS_MACH_IP30_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #endif /* __ASM_MIPS_MACH_IP30_WAR_H */ diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h index c57a9cd2e50b..01475db746ec 100644 --- a/arch/mips/include/asm/mach-ip32/war.h +++ b/arch/mips/include/asm/mach-ip32/war.h @@ -9,6 +9,5 @@ #define __ASM_MIPS_MACH_IP32_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #endif /* __ASM_MIPS_MACH_IP32_WAR_H */ diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h index 73c9e6d84a8f..68b204ff59a6 100644 --- a/arch/mips/include/asm/mach-malta/war.h +++ b/arch/mips/include/asm/mach-malta/war.h @@ -9,6 +9,5 @@ #define __ASM_MIPS_MACH_MIPS_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h index 73c9e6d84a8f..68b204ff59a6 100644 --- a/arch/mips/include/asm/mach-rc32434/war.h +++ b/arch/mips/include/asm/mach-rc32434/war.h @@ -9,6 +9,5 @@ #define __ASM_MIPS_MACH_MIPS_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h index c396a31706ac..093a3894ae41 100644 --- a/arch/mips/include/asm/mach-rm/war.h +++ b/arch/mips/include/asm/mach-rm/war.h @@ -9,6 +9,5 @@ #define __ASM_MIPS_MACH_RM_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #endif /* __ASM_MIPS_MACH_RM_WAR_H */ diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h index fa9bbc228dd7..71eff5bc3f53 100644 --- a/arch/mips/include/asm/mach-sibyte/war.h +++ b/arch/mips/include/asm/mach-sibyte/war.h @@ -15,12 +15,10 @@ extern int sb1250_m3_workaround_needed(void); #endif #define BCM1250_M3_WAR sb1250_m3_workaround_needed() -#define SIBYTE_1956_WAR 1 #else #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #endif diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h index 7213d9334f3f..0dc2beb5bf5a 100644 --- a/arch/mips/include/asm/mach-tx49xx/war.h +++ b/arch/mips/include/asm/mach-tx49xx/war.h @@ -9,6 +9,5 @@ #define __ASM_MIPS_MACH_TX49XX_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */ diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h index 4f4d37b3dd07..2ce5cd61a072 100644 --- a/arch/mips/include/asm/war.h +++ b/arch/mips/include/asm/war.h @@ -86,11 +86,4 @@ #error Check setting of BCM1250_M3_WAR for your platform #endif -/* - * This is a DUART workaround related to glitches around register accesses - */ -#ifndef SIBYTE_1956_WAR -#error Check setting of SIBYTE_1956_WAR for your platform -#endif - #endif /* _ASM_WAR_H */ |