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| author | Jiong Wang <jiong.wang@netronome.com> | 2018-12-03 17:27:54 -0500 |
|---|---|---|
| committer | Alexei Starovoitov <ast@kernel.org> | 2018-12-07 13:29:48 -0800 |
| commit | 17f6c83fb5ebf7db4fcc94a5be4c22d5a7bfe428 (patch) | |
| tree | ce1e3f37bb27154204a32eada3313a634b334775 /arch/mips/include | |
| parent | a06aef4ed5b6f1daa20babb4ad4458392bce5edd (diff) | |
| download | linux-17f6c83fb5ebf7db4fcc94a5be4c22d5a7bfe428.tar.bz2 | |
mips: bpf: fix encoding bug for mm_srlv32_op
For micro-mips, srlv inside POOL32A encoding space should use 0x50
sub-opcode, NOT 0x90.
Some early version ISA doc describes the encoding as 0x90 for both srlv and
srav, this looks to me was a typo. I checked Binutils libopcode
implementation which is using 0x50 for srlv and 0x90 for srav.
v1->v2:
- Keep mm_srlv32_op sorted by value.
Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Acked-by: Song Liu <songliubraving@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/uapi/asm/inst.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h index c05dcf5ab414..273ef58f4d43 100644 --- a/arch/mips/include/uapi/asm/inst.h +++ b/arch/mips/include/uapi/asm/inst.h @@ -369,8 +369,8 @@ enum mm_32a_minor_op { mm_ext_op = 0x02c, mm_pool32axf_op = 0x03c, mm_srl32_op = 0x040, + mm_srlv32_op = 0x050, mm_sra_op = 0x080, - mm_srlv32_op = 0x090, mm_rotr_op = 0x0c0, mm_lwxs_op = 0x118, mm_addu32_op = 0x150, |