diff options
| author | Andrew Bresticker <abrestic@chromium.org> | 2014-09-18 14:47:27 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-11-24 07:44:56 +0100 |
| commit | e9de688dac6534e72d000e9069be2f929a6087be (patch) | |
| tree | e1dd1dbbe4727982177d90a7cd161703a0d7dd16 /arch/mips/include/asm/mips-boards | |
| parent | 4a6a3ea392306b04fc687d4314efba562121cc9a (diff) | |
| download | linux-e9de688dac6534e72d000e9069be2f929a6087be.tar.bz2 | |
irqchip: mips-gic: Support local interrupts
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC
local watchdog and count/compare timer. The remainder are CPU
interrupts which may optionally be re-routed through the GIC.
GIC hardware IRQs 0-6 are now used for local interrupts while
hardware IRQs 7+ are used for external (shared) interrupts.
Note that the 5 CPU interrupts may not be re-routable through
the GIC. In that case mapping will fail and the vectors reported
in C0_IntCtl should be used instead. gic_get_c0_compare_int() and
gic_get_c0_perfcount_int() will return the correct IRQ number to
use for the C0 timer and perfcounter interrupts based on the
routability of those interrupts through the GIC.
A separate irq_chip, with callbacks that mask/unmask the local
interrupt on all CPUs, is used for the C0 timer and performance
counter interrupts since all other platforms do not use the percpu
IRQ API for those interrupts.
Malta, SEAD-3, and the GIC clockevent driver have been updated
to use local interrupts and the R4K clockevent driver has been
updated to poll for C0 timer interrupts through the GIC when
the GIC is present.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Tested-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7819/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mips-boards')
| -rw-r--r-- | arch/mips/include/asm/mips-boards/maltaint.h | 4 | ||||
| -rw-r--r-- | arch/mips/include/asm/mips-boards/sead3int.h | 10 |
2 files changed, 9 insertions, 5 deletions
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index bdd6f392f160..38b06a027437 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -10,6 +10,8 @@ #ifndef _MIPS_MALTAINT_H #define _MIPS_MALTAINT_H +#include <asm/gic.h> + /* * Interrupts 0..15 are used for Malta ISA compatible interrupts */ @@ -61,6 +63,6 @@ #define MSC01E_INT_CPUCTR 11 /* GIC external interrupts */ -#define GIC_INT_I8259A 3 +#define GIC_INT_I8259A GIC_SHARED_TO_HWIRQ(3) #endif /* !(_MIPS_MALTAINT_H) */ diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h index a2e0095440fe..59d6c32c7595 100644 --- a/arch/mips/include/asm/mips-boards/sead3int.h +++ b/arch/mips/include/asm/mips-boards/sead3int.h @@ -10,6 +10,8 @@ #ifndef _MIPS_SEAD3INT_H #define _MIPS_SEAD3INT_H +#include <asm/gic.h> + /* SEAD-3 GIC address space definitions. */ #define GIC_BASE_ADDR 0x1b1c0000 #define GIC_ADDRSPACE_SZ (128 * 1024) @@ -22,9 +24,9 @@ #define CPU_INT_NET 6 /* GIC interrupt offsets */ -#define GIC_INT_NET 0 -#define GIC_INT_UART1 2 -#define GIC_INT_UART0 3 -#define GIC_INT_EHCI 5 +#define GIC_INT_NET GIC_SHARED_TO_HWIRQ(0) +#define GIC_INT_UART1 GIC_SHARED_TO_HWIRQ(2) +#define GIC_INT_UART0 GIC_SHARED_TO_HWIRQ(3) +#define GIC_INT_EHCI GIC_SHARED_TO_HWIRQ(5) #endif /* !(_MIPS_SEAD3INT_H) */ |