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author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-10-16 12:40:55 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-10-16 12:40:55 -0700 |
commit | 09a31a7e3723afd79022d5d3ff3634c2630c2eeb (patch) | |
tree | b9bbf21da582f1c62b0ae8f1e4498754f0198458 /arch/mips/include/asm/mach-ip30/irq.h | |
parent | 847d4287a0c6709fd1ce24002b96d404a6da8b5b (diff) | |
parent | cf3af0a4d3b62ab48e0b90180ea161d0f5d4953f (diff) | |
download | linux-09a31a7e3723afd79022d5d3ff3634c2630c2eeb.tar.bz2 |
Merge tag 'mips_5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer:
- removed support for PNX833x alias NXT_STB22x
- included Ingenic SoC support into generic MIPS kernels
- added support for new Ingenic SoCs
- converted workaround selection to use Kconfig
- replaced old boot mem functions by memblock_*
- enabled COP2 usage in kernel for Loongson64 to make use
of 16byte load/stores possible
- cleanups and fixes
* tag 'mips_5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (92 commits)
MIPS: DEC: Restore bootmem reservation for firmware working memory area
MIPS: dec: fix section mismatch
bcm963xx_tag.h: fix duplicated word
mips: ralink: enable zboot support
MIPS: ingenic: Remove CPU_SUPPORTS_HUGEPAGES
MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bit
MIPS: cpu-probe: introduce exclusive R3k CPU probe
MIPS: cpu-probe: move fpu probing/handling into its own file
MIPS: replace add_memory_region with memblock
MIPS: Loongson64: Clean up numa.c
MIPS: Loongson64: Select SMP in Kconfig to avoid build error
mips: octeon: Add Ubiquiti E200 and E220 boards
MIPS: SGI-IP28: disable use of ll/sc in kernel
MIPS: tx49xx: move tx4939_add_memory_regions into only user
MIPS: pgtable: Remove used PAGE_USERIO define
MIPS: alchemy: Share prom_init implementation
MIPS: alchemy: Fix build breakage, if TOUCHSCREEN_WM97XX is disabled
MIPS: process: include exec.h header in process.c
MIPS: process: Add prototype for function arch_dup_task_struct
MIPS: idle: Add prototype for function check_wait
...
Diffstat (limited to 'arch/mips/include/asm/mach-ip30/irq.h')
-rw-r--r-- | arch/mips/include/asm/mach-ip30/irq.h | 87 |
1 files changed, 0 insertions, 87 deletions
diff --git a/arch/mips/include/asm/mach-ip30/irq.h b/arch/mips/include/asm/mach-ip30/irq.h deleted file mode 100644 index 27ba899c95be..000000000000 --- a/arch/mips/include/asm/mach-ip30/irq.h +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * HEART IRQ defines - * - * Copyright (C) 2009 Johannes Dickgreber <tanzy@gmx.de> - * 2014-2016 Joshua Kinard <kumba@gentoo.org> - * - */ - -#ifndef __ASM_MACH_IP30_IRQ_H -#define __ASM_MACH_IP30_IRQ_H - -/* - * HEART has 64 hardware interrupts, but use 128 to leave room for a few - * software interrupts as well (such as the CPU timer interrupt. - */ -#define NR_IRQS 128 - -extern void __init ip30_install_ipi(void); - -/* - * HEART has 64 interrupt vectors available to it, subdivided into five - * priority levels. They are numbered 0 to 63. - */ -#define HEART_NUM_IRQS 64 - -/* - * These are the five interrupt priority levels and their corresponding - * CPU IPx interrupt pins. - * - * Level 4 - Error Interrupts. - * Level 3 - HEART timer interrupt. - * Level 2 - CPU IPI, CPU debug, power putton, general device interrupts. - * Level 1 - General device interrupts. - * Level 0 - General device GFX flow control interrupts. - */ -#define HEART_L4_INT_MASK 0xfff8000000000000ULL /* IP6 */ -#define HEART_L3_INT_MASK 0x0004000000000000ULL /* IP5 */ -#define HEART_L2_INT_MASK 0x0003ffff00000000ULL /* IP4 */ -#define HEART_L1_INT_MASK 0x00000000ffff0000ULL /* IP3 */ -#define HEART_L0_INT_MASK 0x000000000000ffffULL /* IP2 */ - -/* HEART L0 Interrupts (Low Priority) */ -#define HEART_L0_INT_GENERIC 0 -#define HEART_L0_INT_FLOW_CTRL_HWTR_0 1 -#define HEART_L0_INT_FLOW_CTRL_HWTR_1 2 - -/* HEART L2 Interrupts (High Priority) */ -#define HEART_L2_INT_RESCHED_CPU_0 46 -#define HEART_L2_INT_RESCHED_CPU_1 47 -#define HEART_L2_INT_CALL_CPU_0 48 -#define HEART_L2_INT_CALL_CPU_1 49 - -/* HEART L3 Interrupts (Compare/Counter Timer) */ -#define HEART_L3_INT_TIMER 50 - -/* HEART L4 Interrupts (Errors) */ -#define HEART_L4_INT_XWID_ERR_9 51 -#define HEART_L4_INT_XWID_ERR_A 52 -#define HEART_L4_INT_XWID_ERR_B 53 -#define HEART_L4_INT_XWID_ERR_C 54 -#define HEART_L4_INT_XWID_ERR_D 55 -#define HEART_L4_INT_XWID_ERR_E 56 -#define HEART_L4_INT_XWID_ERR_F 57 -#define HEART_L4_INT_XWID_ERR_XBOW 58 -#define HEART_L4_INT_CPU_BUS_ERR_0 59 -#define HEART_L4_INT_CPU_BUS_ERR_1 60 -#define HEART_L4_INT_CPU_BUS_ERR_2 61 -#define HEART_L4_INT_CPU_BUS_ERR_3 62 -#define HEART_L4_INT_HEART_EXCP 63 - -/* - * Power Switch is wired via BaseIO BRIDGE slot #6. - * - * ACFail is wired via BaseIO BRIDGE slot #7. - */ -#define IP30_POWER_IRQ HEART_L2_INT_POWER_BTN - -#include <asm/mach-generic/irq.h> - -#define IP30_HEART_L0_IRQ (MIPS_CPU_IRQ_BASE + 2) -#define IP30_HEART_L1_IRQ (MIPS_CPU_IRQ_BASE + 3) -#define IP30_HEART_L2_IRQ (MIPS_CPU_IRQ_BASE + 4) -#define IP30_HEART_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 5) -#define IP30_HEART_ERR_IRQ (MIPS_CPU_IRQ_BASE + 6) - -#endif /* __ASM_MACH_IP30_IRQ_H */ |