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authorSteven J. Hill <steven.hill@cavium.com>2016-12-13 14:25:37 -0600
committerRalf Baechle <ralf@linux-mips.org>2017-01-03 16:34:35 +0100
commit3ff72be4c9ce269c5b7adff9b0f912a2df3cb987 (patch)
tree24c14cb9ca8c081670310277b252ea3c9027bf30 /arch/mips/include/asm/mach-cavium-octeon
parent126c1113bf3e6facdd5562064043b9e8fa8c9bf1 (diff)
downloadlinux-3ff72be4c9ce269c5b7adff9b0f912a2df3cb987.tar.bz2
MIPS: Octeon: Enable KASLR
This patch enables KASLR for Octeon systems. The SMP startup code is such that the secondaries monitor the volatile variable 'octeon_processor_relocated_kernel_entry' for any non-zero value. The 'plat_post_relocation hook' is used to set that value to the kernel entry point of the relocated kernel. The secondary CPUs will then jusmp to the new kernel, perform their initialization again and begin waiting for the boot CPU to start them via the relocated loop 'octeon_spin_wait_boot'. Inspired by Steven's code from Cavium. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14669/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-cavium-octeon')
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h15
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c4873e8594ef..c38b38ce5a3d 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -99,9 +99,20 @@
# to begin
#
- # This is the variable where the next core to boot os stored
- PTR_LA t0, octeon_processor_boot
octeon_spin_wait_boot:
+#ifdef CONFIG_RELOCATABLE
+ PTR_LA t0, octeon_processor_relocated_kernel_entry
+ LONG_L t0, (t0)
+ beq zero, t0, 1f
+ nop
+
+ jr t0
+ nop
+1:
+#endif /* CONFIG_RELOCATABLE */
+
+ # This is the variable where the next core to boot is stored
+ PTR_LA t0, octeon_processor_boot
# Get the core id of the next to be booted
LONG_L t1, (t0)
# Keep looping if it isn't me