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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-12 16:25:35 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-12 16:25:35 -0800 |
| commit | 9219a3b9889dbc7dae68e472f239672ff48860b0 (patch) | |
| tree | c6446d63dd7ffb0f118804e354eee3d80041717e /arch/mips/include/asm/io.h | |
| parent | 23ead7291269db3be71b442324381c8d63e5d0b3 (diff) | |
| parent | cde15b5927fea3e1b4de0b277008cf273d8b000b (diff) | |
| download | linux-9219a3b9889dbc7dae68e472f239672ff48860b0.tar.bz2 | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (37 commits)
MIPS: Only write c0_framemask on CPUs which have this register.
MIPS: Alchemy: new userspace suspend interface for development boards.
MIPS: Alchemy: dbdma suspend/resume support.
MIPS: Alchemy: Fix up PM code on Au1550/Au1200
MIPS: Alchemy: move calc_clock function.
MIPS: Alchemy: RTC counter clocksource / clockevent support.
MIPS: make cp0 counter clocksource/event usable as fallback.
MIPS: Alchemy: remove cpu_table.
MIPS: Alchemy: remove get/set_au1x00_lcd_clock().
MIPS: Print irq handler description
MIPS: Alchemy: pb1200: update CPLD cascade irq handler.
MIPS: Alchemy: update core interrupt code.
MIPS: Alchemy: move commandline mangling out of common code
MIPS: Alchemy: devboards: consolidate files
MIPS: Alchemy: Move development board code to common subdirectory
MIPS: Add Cavium OCTEON to arch/mips/Kconfig
MIPS: Add defconfig for Cavium OCTEON.
MIPS: Adjust the dma-common.c platform hooks.
MIPS: Add Cavium OCTEON slot into proper tlb category.
MIPS: Compute branch returns for Cavium OCTEON specific branch instructions.
...
Diffstat (limited to 'arch/mips/include/asm/io.h')
| -rw-r--r-- | arch/mips/include/asm/io.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 501a40b9f18d..436878e4e063 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -295,6 +295,12 @@ static inline void iounmap(const volatile void __iomem *addr) #undef __IS_KSEG1 } +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#define war_octeon_io_reorder_wmb() wmb() +#else +#define war_octeon_io_reorder_wmb() do { } while (0) +#endif + #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ \ static inline void pfx##write##bwlq(type val, \ @@ -303,6 +309,8 @@ static inline void pfx##write##bwlq(type val, \ volatile type *__mem; \ type __val; \ \ + war_octeon_io_reorder_wmb(); \ + \ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ \ __val = pfx##ioswab##bwlq(__mem, val); \ @@ -370,6 +378,8 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ volatile type *__addr; \ type __val; \ \ + war_octeon_io_reorder_wmb(); \ + \ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ \ __val = pfx##ioswab##bwlq(__addr, val); \ @@ -504,8 +514,12 @@ BUILDSTRING(q, u64) #endif +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#define mmiowb() wmb() +#else /* Depends on MIPS II instruction set */ #define mmiowb() asm volatile ("sync" ::: "memory") +#endif static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) { |