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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 15:20:36 -0700
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 15:20:36 -0700
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/ddb5xxx/ddb5477
downloadlinux-1da177e4c3f41524e886b7f1b8a0c1fc7321cac2.tar.bz2
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/ddb5xxx/ddb5477')
-rw-r--r--arch/mips/ddb5xxx/ddb5477/Makefile10
-rw-r--r--arch/mips/ddb5xxx/ddb5477/debug.c160
-rw-r--r--arch/mips/ddb5xxx/ddb5477/int-handler.S75
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq.c199
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq_5477.c168
-rw-r--r--arch/mips/ddb5xxx/ddb5477/kgdb_io.c136
-rw-r--r--arch/mips/ddb5xxx/ddb5477/lcd44780.c92
-rw-r--r--arch/mips/ddb5xxx/ddb5477/lcd44780.h15
-rw-r--r--arch/mips/ddb5xxx/ddb5477/setup.c405
9 files changed, 1260 insertions, 0 deletions
diff --git a/arch/mips/ddb5xxx/ddb5477/Makefile b/arch/mips/ddb5xxx/ddb5477/Makefile
new file mode 100644
index 000000000000..b79b43c9f93b
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for NEC DDB-Vrc5477 board
+#
+
+obj-y += int-handler.o irq.o irq_5477.o setup.o lcd44780.o
+
+obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
+obj-$(CONFIG_KGDB) += kgdb_io.o
+
+EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ddb5xxx/ddb5477/debug.c b/arch/mips/ddb5xxx/ddb5477/debug.c
new file mode 100644
index 000000000000..68919d5f8ffd
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/debug.c
@@ -0,0 +1,160 @@
+/***********************************************************************
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/ddb5477/debug.c
+ * vrc5477 specific debug routines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ ***********************************************************************
+ */
+
+#include <linux/kernel.h>
+
+#include <asm/mipsregs.h>
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+typedef struct {
+ const char *regname;
+ unsigned regaddr;
+} Register;
+
+void jsun_show_regs(char *name, Register *regs)
+{
+ int i;
+
+ printk("\nshow regs: %s\n", name);
+ for(i=0;regs[i].regname!= NULL; i++) {
+ printk("%-16s= %08x\t\t(@%08x)\n",
+ regs[i].regname,
+ *(unsigned *)(regs[i].regaddr),
+ regs[i].regaddr);
+ }
+}
+
+static Register int_regs[] = {
+ {"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0},
+ {"DDB_INTCTRL1", DDB_BASE + DDB_INTCTRL1},
+ {"DDB_INTCTRL2", DDB_BASE + DDB_INTCTRL2},
+ {"DDB_INTCTRL3", DDB_BASE + DDB_INTCTRL3},
+ {"DDB_INT0STAT", DDB_BASE + DDB_INT0STAT},
+ {"DDB_INT1STAT", DDB_BASE + DDB_INT1STAT},
+ {"DDB_INT2STAT", DDB_BASE + DDB_INT2STAT},
+ {"DDB_INT3STAT", DDB_BASE + DDB_INT3STAT},
+ {"DDB_INT4STAT", DDB_BASE + DDB_INT4STAT},
+ {"DDB_NMISTAT", DDB_BASE + DDB_NMISTAT},
+ {"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0},
+ {"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1},
+ {NULL, 0x0}
+};
+
+void vrc5477_show_int_regs()
+{
+ jsun_show_regs("interrupt registers", int_regs);
+ printk("CPU CAUSE = %08x\n", read_c0_cause());
+ printk("CPU STATUS = %08x\n", read_c0_status());
+}
+static Register pdar_regs[] = {
+ {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0},
+ {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1},
+ {"DDB_LCS0", DDB_BASE + DDB_LCS0},
+ {"DDB_LCS1", DDB_BASE + DDB_LCS1},
+ {"DDB_LCS2", DDB_BASE + DDB_LCS2},
+ {"DDB_INTCS", DDB_BASE + DDB_INTCS},
+ {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS},
+ {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
+ {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
+ {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
+ {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
+ {NULL, 0x0}
+};
+void vrc5477_show_pdar_regs(void)
+{
+ jsun_show_regs("PDAR regs", pdar_regs);
+}
+
+static Register bar_regs[] = {
+ {"DDB_BARC0", DDB_BASE + DDB_BARC0},
+ {"DDB_BARM010", DDB_BASE + DDB_BARM010},
+ {"DDB_BARM230", DDB_BASE + DDB_BARM230},
+ {"DDB_BAR00", DDB_BASE + DDB_BAR00},
+ {"DDB_BAR10", DDB_BASE + DDB_BAR10},
+ {"DDB_BAR20", DDB_BASE + DDB_BAR20},
+ {"DDB_BAR30", DDB_BASE + DDB_BAR30},
+ {"DDB_BAR40", DDB_BASE + DDB_BAR40},
+ {"DDB_BAR50", DDB_BASE + DDB_BAR50},
+ {"DDB_BARB0", DDB_BASE + DDB_BARB0},
+ {"DDB_BARC1", DDB_BASE + DDB_BARC1},
+ {"DDB_BARM011", DDB_BASE + DDB_BARM011},
+ {"DDB_BARM231", DDB_BASE + DDB_BARM231},
+ {"DDB_BAR01", DDB_BASE + DDB_BAR01},
+ {"DDB_BAR11", DDB_BASE + DDB_BAR11},
+ {"DDB_BAR21", DDB_BASE + DDB_BAR21},
+ {"DDB_BAR31", DDB_BASE + DDB_BAR31},
+ {"DDB_BAR41", DDB_BASE + DDB_BAR41},
+ {"DDB_BAR51", DDB_BASE + DDB_BAR51},
+ {"DDB_BARB1", DDB_BASE + DDB_BARB1},
+ {NULL, 0x0}
+};
+void vrc5477_show_bar_regs(void)
+{
+ jsun_show_regs("BAR regs", bar_regs);
+}
+
+static Register pci_regs[] = {
+ {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
+ {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
+ {"DDB_PCIINIT00", DDB_BASE + DDB_PCIINIT00},
+ {"DDB_PCIINIT10", DDB_BASE + DDB_PCIINIT10},
+ {"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L},
+ {"DDB_PCICTL0_H", DDB_BASE + DDB_PCICTL0_H},
+ {"DDB_PCIARB0_L", DDB_BASE + DDB_PCIARB0_L},
+ {"DDB_PCIARB0_H", DDB_BASE + DDB_PCIARB0_H},
+ {"DDB_PCISWP0", DDB_BASE + DDB_PCISWP0},
+ {"DDB_PCIERR0", DDB_BASE + DDB_PCIERR0},
+ {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
+ {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
+ {"DDB_PCIINIT01", DDB_BASE + DDB_PCIINIT01},
+ {"DDB_PCIINIT11", DDB_BASE + DDB_PCIINIT11},
+ {"DDB_PCICTL1_L", DDB_BASE + DDB_PCICTL1_L},
+ {"DDB_PCICTL1_H", DDB_BASE + DDB_PCICTL1_H},
+ {"DDB_PCIARB1_L", DDB_BASE + DDB_PCIARB1_L},
+ {"DDB_PCIARB1_H", DDB_BASE + DDB_PCIARB1_H},
+ {"DDB_PCISWP1", DDB_BASE + DDB_PCISWP1},
+ {"DDB_PCIERR1", DDB_BASE + DDB_PCIERR1},
+ {NULL, 0x0}
+};
+void vrc5477_show_pci_regs(void)
+{
+ jsun_show_regs("PCI regs", pci_regs);
+}
+
+static Register lb_regs[] = {
+ {"DDB_LCNFG", DDB_BASE + DDB_LCNFG},
+ {"DDB_LCST0", DDB_BASE + DDB_LCST0},
+ {"DDB_LCST1", DDB_BASE + DDB_LCST1},
+ {"DDB_LCST2", DDB_BASE + DDB_LCST2},
+ {"DDB_ERRADR", DDB_BASE + DDB_ERRADR},
+ {"DDB_ERRCS", DDB_BASE + DDB_ERRCS},
+ {"DDB_BTM", DDB_BASE + DDB_BTM},
+ {"DDB_BCST", DDB_BASE + DDB_BCST},
+ {NULL, 0x0}
+};
+void vrc5477_show_lb_regs(void)
+{
+ jsun_show_regs("Local Bus regs", lb_regs);
+}
+
+void vrc5477_show_all_regs(void)
+{
+ vrc5477_show_pdar_regs();
+ vrc5477_show_pci_regs();
+ vrc5477_show_bar_regs();
+ vrc5477_show_int_regs();
+ vrc5477_show_lb_regs();
+}
diff --git a/arch/mips/ddb5xxx/ddb5477/int-handler.S b/arch/mips/ddb5xxx/ddb5477/int-handler.S
new file mode 100644
index 000000000000..a2502a14400e
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/int-handler.S
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * First-level interrupt dispatcher for ddb5477
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+#include <asm/ddb5xxx/ddb5477.h>
+
+/*
+ * first level interrupt dispatcher for ocelot board -
+ * We check for the timer first, then check PCI ints A and D.
+ * Then check for serial IRQ and fall through.
+ */
+ .align 5
+ NESTED(ddb5477_handle_int, PT_SIZE, sp)
+ SAVE_ALL
+ CLI
+ .set at
+ .set noreorder
+ mfc0 t0, CP0_CAUSE
+ mfc0 t2, CP0_STATUS
+
+ and t0, t2
+
+ andi t1, t0, STATUSF_IP7 /* cpu timer */
+ bnez t1, ll_cputimer_irq
+ andi t1, t0, (STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6 )
+ bnez t1, ll_vrc5477_irq
+ andi t1, t0, STATUSF_IP0 /* software int 0 */
+ bnez t1, ll_cpu_ip0
+ andi t1, t0, STATUSF_IP1 /* software int 1 */
+ bnez t1, ll_cpu_ip1
+ nop
+ .set reorder
+
+ /* wrong alarm or masked ... */
+ j spurious_interrupt
+ nop
+ END(ddb5477_handle_int)
+
+ .align 5
+
+ll_vrc5477_irq:
+ move a0, sp
+ jal vrc5477_irq_dispatch
+ j ret_from_irq
+
+ll_cputimer_irq:
+ li a0, CPU_IRQ_BASE + 7
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+
+ll_cpu_ip0:
+ li a0, CPU_IRQ_BASE + 0
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+ll_cpu_ip1:
+ li a0, CPU_IRQ_BASE + 1
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
new file mode 100644
index 000000000000..5f027bfa4af8
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/irq.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/ddb5477/irq.c
+ * The irq setup and misc routines for DDB5476.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+
+#include <asm/i8259.h>
+#include <asm/system.h>
+#include <asm/mipsregs.h>
+#include <asm/debug.h>
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+
+/*
+ * IRQ mapping
+ *
+ * 0-7: 8 CPU interrupts
+ * 0 - software interrupt 0
+ * 1 - software interrupt 1
+ * 2 - most Vrc5477 interrupts are routed to this pin
+ * 3 - (optional) some other interrupts routed to this pin for debugg
+ * 4 - not used
+ * 5 - not used
+ * 6 - not used
+ * 7 - cpu timer (used by default)
+ *
+ * 8-39: 32 Vrc5477 interrupt sources
+ * (refer to the Vrc5477 manual)
+ */
+
+#define PCI0 DDB_INTPPES0
+#define PCI1 DDB_INTPPES1
+
+#define ACTIVE_LOW 1
+#define ACTIVE_HIGH 0
+
+#define LEVEL_SENSE 2
+#define EDGE_TRIGGER 0
+
+#define INTA 0
+#define INTB 1
+#define INTC 2
+#define INTD 3
+#define INTE 4
+
+static inline void
+set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
+{
+ u32 reg_value;
+ u32 reg_bitmask;
+
+ reg_value = ddb_in32(pci);
+ reg_bitmask = 0x3 << (intn * 2);
+
+ reg_value &= ~reg_bitmask;
+ reg_value |= (active | trigger) << (intn * 2);
+ ddb_out32(pci, reg_value);
+}
+
+extern void vrc5477_irq_init(u32 base);
+extern void mips_cpu_irq_init(u32 base);
+extern asmlinkage void ddb5477_handle_int(void);
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
+
+void __init arch_init_irq(void)
+{
+ /* by default, we disable all interrupts and route all vrc5477
+ * interrupts to pin 0 (irq 2) */
+ ddb_out32(DDB_INTCTRL0, 0);
+ ddb_out32(DDB_INTCTRL1, 0);
+ ddb_out32(DDB_INTCTRL2, 0);
+ ddb_out32(DDB_INTCTRL3, 0);
+
+ clear_c0_status(0xff00);
+ set_c0_status(0x0400);
+
+ /* setup PCI interrupt attributes */
+ set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
+ if (mips_machtype == MACH_NEC_ROCKHOPPERII)
+ set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
+ else
+ set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
+
+ set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
+
+ /*
+ * for debugging purpose, we enable several error interrupts
+ * and route them to pin 1. (IP3)
+ */
+ /* cpu parity check - 0 */
+ ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
+ /* cpu no-target decode - 1 */
+ ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
+ /* local bus read time-out - 7 */
+ ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
+ /* PCI SERR# - 14 */
+ ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
+ /* PCI internal error - 15 */
+ ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
+ /* IOPCI SERR# - 30 */
+ ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
+ /* IOPCI internal error - 31 */
+ ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
+
+ /* init all controllers */
+ init_i8259_irqs();
+ mips_cpu_irq_init(CPU_IRQ_BASE);
+ vrc5477_irq_init(VRC5477_IRQ_BASE);
+
+
+ /* setup cascade interrupts */
+ setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
+ setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
+
+ /* hook up the first-level interrupt handler */
+ set_except_vector(0, ddb5477_handle_int);
+}
+
+u8 i8259_interrupt_ack(void)
+{
+ u8 irq;
+ u32 reg;
+
+ /* Set window 0 for interrupt acknowledge */
+ reg = ddb_in32(DDB_PCIINIT10);
+
+ ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
+ irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
+ ddb_out32(DDB_PCIINIT10, reg);
+
+ /* i8259.c set the base vector to be 0x0 */
+ return irq + I8259_IRQ_BASE;
+}
+/*
+ * the first level int-handler will jump here if it is a vrc5477 irq
+ */
+#define NUM_5477_IRQS 32
+asmlinkage void
+vrc5477_irq_dispatch(struct pt_regs *regs)
+{
+ u32 intStatus;
+ u32 bitmask;
+ u32 i;
+
+ db_assert(ddb_in32(DDB_INT2STAT) == 0);
+ db_assert(ddb_in32(DDB_INT3STAT) == 0);
+ db_assert(ddb_in32(DDB_INT4STAT) == 0);
+ db_assert(ddb_in32(DDB_NMISTAT) == 0);
+
+ if (ddb_in32(DDB_INT1STAT) != 0) {
+#if defined(CONFIG_RUNTIME_DEBUG)
+ vrc5477_show_int_regs();
+#endif
+ panic("error interrupt has happened.");
+ }
+
+ intStatus = ddb_in32(DDB_INT0STAT);
+
+ if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
+ /* check for i8259 interrupts */
+ if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
+ int i8259_irq = i8259_interrupt_ack();
+ do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
+ return;
+ }
+ }
+
+ for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
+ /* do we need to "and" with the int mask? */
+ if (intStatus & bitmask) {
+ do_IRQ(VRC5477_IRQ_BASE + i, regs);
+ return;
+ }
+ }
+}
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
new file mode 100644
index 000000000000..0d5e706207ec
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/ddb5477/irq_5477.c
+ * This file defines the irq handler for Vrc5477.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+/*
+ * Vrc5477 defines 32 IRQs.
+ *
+ * This file exports one function:
+ * vrc5477_irq_init(u32 irq_base);
+ */
+
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+
+#include <asm/debug.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+/* number of total irqs supported by Vrc5477 */
+#define NUM_5477_IRQ 32
+
+static int vrc5477_irq_base = -1;
+
+
+static void
+vrc5477_irq_enable(unsigned int irq)
+{
+ db_assert(vrc5477_irq_base != -1);
+ db_assert(irq >= vrc5477_irq_base);
+ db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
+
+ ll_vrc5477_irq_enable(irq - vrc5477_irq_base);
+}
+
+static void
+vrc5477_irq_disable(unsigned int irq)
+{
+ db_assert(vrc5477_irq_base != -1);
+ db_assert(irq >= vrc5477_irq_base);
+ db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
+
+ ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
+}
+
+static unsigned int vrc5477_irq_startup(unsigned int irq)
+{
+ vrc5477_irq_enable(irq);
+ return 0;
+}
+
+#define vrc5477_irq_shutdown vrc5477_irq_disable
+
+static void
+vrc5477_irq_ack(unsigned int irq)
+{
+ db_assert(vrc5477_irq_base != -1);
+ db_assert(irq >= vrc5477_irq_base);
+ db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
+
+ /* clear the interrupt bit */
+ /* some irqs require the driver to clear the sources */
+ ddb_out32(DDB_INTCLR32, 1 << (irq - vrc5477_irq_base));
+
+ /* disable interrupt - some handler will re-enable the irq
+ * and if the interrupt is leveled, we will have infinite loop
+ */
+ ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
+}
+
+static void
+vrc5477_irq_end(unsigned int irq)
+{
+ db_assert(vrc5477_irq_base != -1);
+ db_assert(irq >= vrc5477_irq_base);
+ db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
+
+ if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
+}
+
+hw_irq_controller vrc5477_irq_controller = {
+ "vrc5477_irq",
+ vrc5477_irq_startup,
+ vrc5477_irq_shutdown,
+ vrc5477_irq_enable,
+ vrc5477_irq_disable,
+ vrc5477_irq_ack,
+ vrc5477_irq_end,
+ NULL /* no affinity stuff for UP */
+};
+
+void __init vrc5477_irq_init(u32 irq_base)
+{
+ u32 i;
+
+ for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &vrc5477_irq_controller;
+ }
+
+ vrc5477_irq_base = irq_base;
+}
+
+void ll_vrc5477_irq_route(int vrc5477_irq, int ip)
+{
+ u32 reg_value;
+ u32 reg_bitmask;
+ u32 reg_index;
+
+ db_assert(vrc5477_irq >= 0);
+ db_assert(vrc5477_irq < NUM_5477_IRQ);
+ db_assert(ip >= 0);
+ db_assert((ip < 5) || (ip == 6));
+
+ reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
+ reg_value = ddb_in32(reg_index);
+ reg_bitmask = 7 << (vrc5477_irq % 8 * 4);
+ reg_value &= ~reg_bitmask;
+ reg_value |= ip << (vrc5477_irq % 8 * 4);
+ ddb_out32(reg_index, reg_value);
+}
+
+void ll_vrc5477_irq_enable(int vrc5477_irq)
+{
+ u32 reg_value;
+ u32 reg_bitmask;
+ u32 reg_index;
+
+ db_assert(vrc5477_irq >= 0);
+ db_assert(vrc5477_irq < NUM_5477_IRQ);
+
+ reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
+ reg_value = ddb_in32(reg_index);
+ reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
+ db_assert((reg_value & reg_bitmask) == 0);
+ ddb_out32(reg_index, reg_value | reg_bitmask);
+}
+
+void ll_vrc5477_irq_disable(int vrc5477_irq)
+{
+ u32 reg_value;
+ u32 reg_bitmask;
+ u32 reg_index;
+
+ db_assert(vrc5477_irq >= 0);
+ db_assert(vrc5477_irq < NUM_5477_IRQ);
+
+ reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
+ reg_value = ddb_in32(reg_index);
+ reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
+
+ /* we assert that the interrupt is enabled (perhaps over-zealous) */
+ db_assert( (reg_value & reg_bitmask) != 0);
+ ddb_out32(reg_index, reg_value & ~reg_bitmask);
+}
diff --git a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
new file mode 100644
index 000000000000..1d18d590495b
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
@@ -0,0 +1,136 @@
+/*
+ * kgdb io functions for DDB5477. We use the second serial port (upper one).
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+/* ======================= CONFIG ======================== */
+
+/* [jsun] we use the second serial port for kdb */
+#define BASE 0xbfa04240
+#define MAX_BAUD 115200
+
+/* distance in bytes between two serial registers */
+#define REG_OFFSET 8
+
+/*
+ * 0 - kgdb does serial init
+ * 1 - kgdb skip serial init
+ */
+static int remoteDebugInitialized = 0;
+
+/*
+ * the default baud rate *if* kgdb does serial init
+ */
+#define BAUD_DEFAULT UART16550_BAUD_38400
+
+/* ======================= END OF CONFIG ======================== */
+
+typedef unsigned char uint8;
+typedef unsigned int uint32;
+
+#define UART16550_BAUD_2400 2400
+#define UART16550_BAUD_4800 4800
+#define UART16550_BAUD_9600 9600
+#define UART16550_BAUD_19200 19200
+#define UART16550_BAUD_38400 38400
+#define UART16550_BAUD_57600 57600
+#define UART16550_BAUD_115200 115200
+
+#define UART16550_PARITY_NONE 0
+#define UART16550_PARITY_ODD 0x08
+#define UART16550_PARITY_EVEN 0x18
+#define UART16550_PARITY_MARK 0x28
+#define UART16550_PARITY_SPACE 0x38
+
+#define UART16550_DATA_5BIT 0x0
+#define UART16550_DATA_6BIT 0x1
+#define UART16550_DATA_7BIT 0x2
+#define UART16550_DATA_8BIT 0x3
+
+#define UART16550_STOP_1BIT 0x0
+#define UART16550_STOP_2BIT 0x4
+
+/* register offset */
+#define OFS_RCV_BUFFER 0
+#define OFS_TRANS_HOLD 0
+#define OFS_SEND_BUFFER 0
+#define OFS_INTR_ENABLE (1*REG_OFFSET)
+#define OFS_INTR_ID (2*REG_OFFSET)
+#define OFS_DATA_FORMAT (3*REG_OFFSET)
+#define OFS_LINE_CONTROL (3*REG_OFFSET)
+#define OFS_MODEM_CONTROL (4*REG_OFFSET)
+#define OFS_RS232_OUTPUT (4*REG_OFFSET)
+#define OFS_LINE_STATUS (5*REG_OFFSET)
+#define OFS_MODEM_STATUS (6*REG_OFFSET)
+#define OFS_RS232_INPUT (6*REG_OFFSET)
+#define OFS_SCRATCH_PAD (7*REG_OFFSET)
+
+#define OFS_DIVISOR_LSB (0*REG_OFFSET)
+#define OFS_DIVISOR_MSB (1*REG_OFFSET)
+
+
+/* memory-mapped read/write of the port */
+#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
+#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
+
+void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+{
+ /* disable interrupts */
+ UART16550_WRITE(OFS_INTR_ENABLE, 0);
+
+ /* set up buad rate */
+ {
+ uint32 divisor;
+
+ /* set DIAB bit */
+ UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+ /* set divisor */
+ divisor = MAX_BAUD / baud;
+ UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+ UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
+
+ /* clear DIAB bit */
+ UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+ }
+
+ /* set data format */
+ UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+}
+
+
+uint8 getDebugChar(void)
+{
+ if (!remoteDebugInitialized) {
+ remoteDebugInitialized = 1;
+ debugInit(BAUD_DEFAULT,
+ UART16550_DATA_8BIT,
+ UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+ }
+
+ while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
+ return UART16550_READ(OFS_RCV_BUFFER);
+}
+
+
+int putDebugChar(uint8 byte)
+{
+ if (!remoteDebugInitialized) {
+ remoteDebugInitialized = 1;
+ debugInit(BAUD_DEFAULT,
+ UART16550_DATA_8BIT,
+ UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+ }
+
+ while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
+ UART16550_WRITE(OFS_SEND_BUFFER, byte);
+ return 1;
+}
diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.c b/arch/mips/ddb5xxx/ddb5477/lcd44780.c
new file mode 100644
index 000000000000..35c6c22610c5
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/lcd44780.c
@@ -0,0 +1,92 @@
+/*
+ * lcd44780.c
+ * Simple "driver" for a memory-mapped 44780-style LCD display.
+ *
+ * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#define LCD44780_COMMAND ((volatile unsigned char *)0xbe020000)
+#define LCD44780_DATA ((volatile unsigned char *)0xbe020001)
+
+#define LCD44780_4BIT_1LINE 0x20
+#define LCD44780_4BIT_2LINE 0x28
+#define LCD44780_8BIT_1LINE 0x30
+#define LCD44780_8BIT_2LINE 0x38
+#define LCD44780_MODE_DEC 0x04
+#define LCD44780_MODE_DEC_SHIFT 0x05
+#define LCD44780_MODE_INC 0x06
+#define LCD44780_MODE_INC_SHIFT 0x07
+#define LCD44780_SCROLL_LEFT 0x18
+#define LCD44780_SCROLL_RIGHT 0x1e
+#define LCD44780_CURSOR_UNDERLINE 0x0e
+#define LCD44780_CURSOR_BLOCK 0x0f
+#define LCD44780_CURSOR_OFF 0x0c
+#define LCD44780_CLEAR 0x01
+#define LCD44780_BLANK 0x08
+#define LCD44780_RESTORE 0x0c // Same as CURSOR_OFF
+#define LCD44780_HOME 0x02
+#define LCD44780_LEFT 0x10
+#define LCD44780_RIGHT 0x14
+
+void lcd44780_wait(void)
+{
+ int i, j;
+ for(i=0; i < 400; i++)
+ for(j=0; j < 10000; j++);
+}
+
+void lcd44780_command(unsigned char c)
+{
+ *LCD44780_COMMAND = c;
+ lcd44780_wait();
+}
+
+void lcd44780_data(unsigned char c)
+{
+ *LCD44780_DATA = c;
+ lcd44780_wait();
+}
+
+void lcd44780_puts(const char* s)
+{
+ int i,j;
+ int pos = 0;
+
+ lcd44780_command(LCD44780_CLEAR);
+ while(*s) {
+ lcd44780_data(*s);
+ s++;
+ pos++;
+ if (pos == 8) {
+ /* We must write 32 of spaces to get cursor to 2nd line */
+ for (j=0; j<32; j++) {
+ lcd44780_data(' ');
+ }
+ }
+ if (pos == 16) {
+ /* We have filled all 16 character positions, so stop
+ outputing data */
+ break;
+ }
+ }
+#ifdef LCD44780_PUTS_PAUSE
+ for(i = 1; i < 2000; i++)
+ lcd44780_wait();
+#endif
+}
+
+void lcd44780_init(void)
+{
+ // The display on the RockHopper is physically a single
+ // 16 char line (two 8 char lines concatenated). bdl
+ lcd44780_command(LCD44780_8BIT_2LINE);
+ lcd44780_command(LCD44780_MODE_INC);
+ lcd44780_command(LCD44780_CURSOR_BLOCK);
+ lcd44780_command(LCD44780_CLEAR);
+}
diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.h b/arch/mips/ddb5xxx/ddb5477/lcd44780.h
new file mode 100644
index 000000000000..cf2f0f71eee5
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/lcd44780.h
@@ -0,0 +1,15 @@
+/*
+ * lcd44780.h
+ * Simple "driver" for a memory-mapped 44780-style LCD display.
+ *
+ * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+void lcd44780_puts(const char* s);
+void lcd44780_init(void);
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c
new file mode 100644
index 000000000000..15c6e543b56f
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/setup.c
@@ -0,0 +1,405 @@
+/*
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ *
+ * arch/mips/ddb5xxx/ddb5477/setup.c
+ * Setup file for DDB5477.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/ide.h>
+#include <linux/fs.h>
+#include <linux/ioport.h>
+#include <linux/param.h> /* for HZ */
+#include <linux/major.h>
+#include <linux/kdev_t.h>
+#include <linux/root_dev.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/time.h>
+#include <asm/bcache.h>
+#include <asm/irq.h>
+#include <asm/reboot.h>
+#include <asm/gdb-stub.h>
+#include <asm/traps.h>
+#include <asm/debug.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+#include "lcd44780.h"
+
+
+#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
+
+#define SP_TIMER_BASE DDB_SPT1CTRL_L
+#define SP_TIMER_IRQ VRC5477_IRQ_SPT1
+
+static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
+
+static void ddb_machine_restart(char *command)
+{
+ static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
+
+ u32 t;
+
+ /* PCI cold reset */
+ ddb_pci_reset_bus();
+
+ /* CPU cold reset */
+ t = ddb_in32(DDB_CPUSTAT);
+ db_assert((t&1));
+ ddb_out32(DDB_CPUSTAT, t);
+
+ /* Call the PROM */
+ back_to_prom();
+}
+
+static void ddb_machine_halt(void)
+{
+ printk("DDB Vrc-5477 halted.\n");
+ while (1);
+}
+
+static void ddb_machine_power_off(void)
+{
+ printk("DDB Vrc-5477 halted. Please turn off the power.\n");
+ while (1);
+}
+
+extern void rtc_ds1386_init(unsigned long base);
+
+static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
+{
+ unsigned int freq;
+ unsigned char c;
+ unsigned int t1, t2;
+ unsigned i;
+
+ ddb_out32(SP_TIMER_BASE, 0xffffffff);
+ ddb_out32(SP_TIMER_BASE+4, 0x1);
+ ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
+
+ /* check if rtc is running */
+ c= *(volatile unsigned char*)rtc_base;
+ for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
+ if (c == *(volatile unsigned char*)rtc_base) {
+ printk("Failed to detect bus frequency. Use default 83.3MHz.\n");
+ return 83333000;
+ }
+
+ c= *(volatile unsigned char*)rtc_base;
+ while (c == *(volatile unsigned char*)rtc_base);
+ /* we are now at the turn of 1/100th second, if no error. */
+ t1 = ddb_in32(SP_TIMER_BASE+8);
+
+ for (i=0; i< 10; i++) {
+ c= *(volatile unsigned char*)rtc_base;
+ while (c == *(volatile unsigned char*)rtc_base);
+ /* we are now at the turn of another 1/100th second */
+ t2 = ddb_in32(SP_TIMER_BASE+8);
+ }
+
+ ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */
+
+ freq = (t1 - t2)*10;
+ printk("DDB bus frequency detection : %u \n", freq);
+ return freq;
+}
+
+static void __init ddb_time_init(void)
+{
+ unsigned long rtc_base;
+ unsigned int i;
+
+ /* we have ds1396 RTC chip */
+ if (mips_machtype == MACH_NEC_ROCKHOPPER
+ || mips_machtype == MACH_NEC_ROCKHOPPERII) {
+ rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
+ } else {
+ rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
+ }
+ rtc_ds1386_init(rtc_base);
+
+ /* do we need to do run-time detection of bus speed? */
+ if (bus_frequency == 0) {
+ bus_frequency = detect_bus_frequency(rtc_base);
+ }
+
+ /* mips_hpt_frequency is 1/2 of the cpu core freq */
+ i = (read_c0_config() >> 28 ) & 7;
+ if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
+ i = 4;
+ mips_hpt_frequency = bus_frequency*(i+4)/4;
+}
+
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+
+static void __init ddb_timer_setup(struct irqaction *irq)
+{
+#if defined(USE_CPU_COUNTER_TIMER)
+
+ /* we are using the cpu counter for timer interrupts */
+ setup_irq(CPU_IRQ_BASE + 7, irq);
+
+#else
+
+ /* if we use Special purpose timer 1 */
+ ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
+ ddb_out32(SP_TIMER_BASE+4, 0x1);
+ setup_irq(SP_TIMER_IRQ, irq);
+
+#endif
+}
+
+static void ddb5477_board_init(void);
+
+extern struct pci_controller ddb5477_ext_controller;
+extern struct pci_controller ddb5477_io_controller;
+
+static int ddb5477_setup(void)
+{
+ /* initialize board - we don't trust the loader */
+ ddb5477_board_init();
+
+ set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
+
+ board_time_init = ddb_time_init;
+ board_timer_setup = ddb_timer_setup;
+
+ _machine_restart = ddb_machine_restart;
+ _machine_halt = ddb_machine_halt;
+ _machine_power_off = ddb_machine_power_off;
+
+ /* setup resource limits */
+ ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
+ iomem_resource.end = 0xffffffff;
+
+ /* Reboot on panic */
+ panic_timeout = 180;
+
+ register_pci_controller (&ddb5477_ext_controller);
+ register_pci_controller (&ddb5477_io_controller);
+
+ return 0;
+}
+
+early_initcall(ddb5477_setup);
+
+static void __init ddb5477_board_init(void)
+{
+ /* ----------- setup PDARs ------------ */
+
+ /* SDRAM should have been set */
+ db_assert(ddb_in32(DDB_SDRAM0) ==
+ ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
+
+ /* SDRAM1 should be turned off. What is this for anyway ? */
+ db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
+
+ /* Setup local bus. */
+
+ /* Flash U12 PDAR and timing. */
+ ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
+ ddb_out32(DDB_LCST0, 0x00090842);
+
+ /* We need to setup LCS1 and LCS2 differently based on the
+ board_version */
+ if (mips_machtype == MACH_NEC_ROCKHOPPER) {
+ /* Flash U13 PDAR and timing. */
+ ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
+ ddb_out32(DDB_LCST1, 0x00090842);
+
+ /* EPLD (NVRAM, switch, LCD, and mezzanie). */
+ ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
+ } else {
+ /* misc */
+ ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
+ /* mezzanie (?) */
+ ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
+ }
+
+ /* verify VRC5477 base addr */
+ db_assert(ddb_in32(DDB_VRC5477) ==
+ ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
+
+ /* verify BOOT ROM addr */
+ db_assert(ddb_in32(DDB_BOOTCS) ==
+ ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
+
+ /* setup PCI windows - window0 for MEM/config, window1 for IO */
+ ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
+
+ /* ------------ reset PCI bus and BARs ----------------- */
+ ddb_pci_reset_bus();
+
+ ddb_out32(DDB_BARM010, 0x00000008);
+ ddb_out32(DDB_BARM011, 0x00000008);
+
+ ddb_out32(DDB_BARC0, 0xffffffff);
+ ddb_out32(DDB_BARM230, 0xffffffff);
+ ddb_out32(DDB_BAR00, 0xffffffff);
+ ddb_out32(DDB_BAR10, 0xffffffff);
+ ddb_out32(DDB_BAR20, 0xffffffff);
+ ddb_out32(DDB_BAR30, 0xffffffff);
+ ddb_out32(DDB_BAR40, 0xffffffff);
+ ddb_out32(DDB_BAR50, 0xffffffff);
+ ddb_out32(DDB_BARB0, 0xffffffff);
+
+ ddb_out32(DDB_BARC1, 0xffffffff);
+ ddb_out32(DDB_BARM231, 0xffffffff);
+ ddb_out32(DDB_BAR01, 0xffffffff);
+ ddb_out32(DDB_BAR11, 0xffffffff);
+ ddb_out32(DDB_BAR21, 0xffffffff);
+ ddb_out32(DDB_BAR31, 0xffffffff);
+ ddb_out32(DDB_BAR41, 0xffffffff);
+ ddb_out32(DDB_BAR51, 0xffffffff);
+ ddb_out32(DDB_BARB1, 0xffffffff);
+
+ /*
+ * We use pci master register 0 for memory space / config space
+ * And we use register 1 for IO space.
+ * Note that for memory space, we bump up the pci base address
+ * so that we have 1:1 mapping between PCI memory and cpu physical.
+ * For PCI IO space, it starts from 0 in PCI IO space but with
+ * DDB_xx_IO_BASE in CPU physical address space.
+ */
+ ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
+ DDB_PCI_ACCESS_32);
+ ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
+
+ ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
+ DDB_PCI_ACCESS_32);
+ ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
+ DDB_PCI_ACCESS_32);
+
+
+ /* PCI cross window should be set properly */
+ ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
+
+ if (mips_machtype == MACH_NEC_ROCKHOPPER
+ || mips_machtype == MACH_NEC_ROCKHOPPERII) {
+ /* Disable bus diagnostics. */
+ ddb_out32(DDB_PCICTL0_L, 0);
+ ddb_out32(DDB_PCICTL0_H, 0);
+ ddb_out32(DDB_PCICTL1_L, 0);
+ ddb_out32(DDB_PCICTL1_H, 0);
+ }
+
+ if (mips_machtype == MACH_NEC_ROCKHOPPER) {
+ u16 vid;
+ struct pci_bus bus;
+ struct pci_dev dev_m1533;
+ extern struct pci_ops ddb5477_ext_pci_ops;
+
+ bus.parent = NULL; /* we scan the top level only */
+ bus.ops = &ddb5477_ext_pci_ops;
+ dev_m1533.bus = &bus;
+ dev_m1533.sysdata = NULL;
+ dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
+ pci_read_config_word(&dev_m1533, 0, &vid);
+ if (vid == PCI_VENDOR_ID_AL) {
+ printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
+ mips_machtype = MACH_NEC_ROCKHOPPERII;
+ }
+ }
+
+ /* enable USB input buffers */
+ ddb_out32(DDB_PIBMISC, 0x00000007);
+
+ /* For dual-function pins, make them all non-GPIO */
+ ddb_out32(DDB_GIUFUNSEL, 0x0);
+ // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */
+
+ if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
+
+ /* enable IDE controller on Ali chip (south bridge) */
+ u8 temp8;
+ struct pci_bus bus;
+ struct pci_dev dev_m1533;
+ struct pci_dev dev_m5229;
+ extern struct pci_ops ddb5477_ext_pci_ops;
+
+ /* Setup M1535 registers */
+ bus.parent = NULL; /* we scan the top level only */
+ bus.ops = &ddb5477_ext_pci_ops;
+ dev_m1533.bus = &bus;
+ dev_m1533.sysdata = NULL;
+ dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
+
+ /* setup IDE controller
+ * enable IDE controller (bit 6 - 1)
+ * IDE IDSEL to be addr:A15 (bit 4:5 - 11)
+ * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
+ * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
+ */
+ pci_write_config_byte(&dev_m1533, 0x58, 0x74);
+
+ /*
+ * positive decode (bit6 -0)
+ * enable IDE controler interrupt (bit 4 -1)
+ * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
+ */
+ pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
+
+ /* Setup M5229 registers */
+ dev_m5229.bus = &bus;
+ dev_m5229.sysdata = NULL;
+ dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
+
+ /*
+ * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
+ * M5229 IDSEL is addr:15; see above setting
+ */
+ pci_read_config_byte(&dev_m5229, 0x50, &temp8);
+ pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
+
+ /*
+ * enable bus master (bit 2) and IO decoding (bit 0)
+ */
+ pci_read_config_byte(&dev_m5229, 0x04, &temp8);
+ pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
+
+ /*
+ * enable native, copied from arch/ppc/k2boot/head.S
+ * TODO - need volatile, need to be portable
+ */
+ pci_write_config_byte(&dev_m5229, 0x09, 0xef);
+
+ /* Set Primary Channel Command Block Timing */
+ pci_write_config_byte(&dev_m5229, 0x59, 0x31);
+
+ /*
+ * Enable primary channel 40-pin cable
+ * M5229 register 0x4a (bit 0)
+ */
+ pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
+ pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
+ }
+
+ if (mips_machtype == MACH_NEC_ROCKHOPPER
+ || mips_machtype == MACH_NEC_ROCKHOPPERII) {
+ printk("lcd44780: initializing\n");
+ lcd44780_init();
+ lcd44780_puts("MontaVista Linux");
+ }
+}