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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2006-10-14 00:25:04 +0900
committerRalf Baechle <ralf@linux-mips.org>2006-11-30 01:14:43 +0000
commit56ae58333031bb0564c141f955d1e42276cade55 (patch)
treede1e272dbebb07f268b6d9bc1fd553279f517ac8 /arch/mips/cobalt
parent4e3884fc83f40b5daabceeee3a428a8ebebbbe4a (diff)
downloadlinux-56ae58333031bb0564c141f955d1e42276cade55.tar.bz2
[MIPS] Rewrite GALILEO_INL/GALILEO_OUTL to GT_READ/GT_WRITE
This patch has rewritten GALILEO_INL/GALILEO_OUTL using GT_READ/GT_WRITE. This patch tested on Cobalt Qube2. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cobalt')
-rw-r--r--arch/mips/cobalt/irq.c31
-rw-r--r--arch/mips/cobalt/setup.c16
2 files changed, 22 insertions, 25 deletions
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 82e569d5b02c..4c46f0e73783 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -45,25 +45,22 @@ static inline void galileo_irq(void)
{
unsigned int mask, pending, devfn;
- mask = GALILEO_INL(GT_INTRMASK_OFS);
- pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;
+ mask = GT_READ(GT_INTRMASK_OFS);
+ pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
- if (pending & GALILEO_INTR_T0EXP) {
-
- GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
+ if (pending & GT_INTR_T0EXP_MSK) {
+ GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
do_IRQ(COBALT_GALILEO_IRQ);
-
- } else if (pending & GALILEO_INTR_RETRY_CTR) {
-
- devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;
- GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);
- printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",
- PCI_SLOT(devfn), PCI_FUNC(devfn));
-
+ } else if (pending & GT_INTR_RETRYCTR0_MSK) {
+ devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
+ GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
+ printk(KERN_WARNING
+ "Galileo: PCI retry count exceeded (%02x.%u)\n",
+ PCI_SLOT(devfn), PCI_FUNC(devfn));
} else {
-
- GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);
- printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);
+ GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
+ printk(KERN_WARNING
+ "Galileo: masking unexpected interrupt %08x\n", pending);
}
}
@@ -104,7 +101,7 @@ void __init arch_init_irq(void)
* Mask all Galileo interrupts. The Galileo
* handler is set in cobalt_timer_setup()
*/
- GALILEO_OUTL(0, GT_INTRMASK_OFS);
+ GT_WRITE(GT_INTRMASK_OFS, 0);
init_i8259_irqs(); /* 0 ... 15 */
mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index bf9dc72b9720..e8f0f20b852d 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -51,23 +51,23 @@ const char *get_system_type(void)
void __init plat_timer_setup(struct irqaction *irq)
{
/* Load timer value for HZ (TCLK is 50MHz) */
- GALILEO_OUTL(50*1000*1000 / HZ, GT_TC0_OFS);
+ GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
/* Enable timer */
- GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS);
+ GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
/* Register interrupt */
setup_irq(COBALT_GALILEO_IRQ, irq);
/* Enable interrupt */
- GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
+ GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
}
extern struct pci_ops gt64111_pci_ops;
static struct resource cobalt_mem_resource = {
- .start = GT64111_MEM_BASE,
- .end = GT64111_MEM_END,
+ .start = GT_DEF_PCI0_MEM0_BASE,
+ .end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
.name = "PCI memory",
.flags = IORESOURCE_MEM
};
@@ -115,7 +115,7 @@ static struct pci_controller cobalt_pci_controller = {
.mem_resource = &cobalt_mem_resource,
.mem_offset = 0,
.io_resource = &cobalt_io_resource,
- .io_offset = 0 - GT64111_IO_BASE
+ .io_offset = 0 - GT_DEF_PCI0_IO_BASE,
};
void __init plat_mem_setup(void)
@@ -128,7 +128,7 @@ void __init plat_mem_setup(void)
_machine_halt = cobalt_machine_halt;
pm_power_off = cobalt_machine_power_off;
- set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
+ set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
/* I/O port resource must include UART and LCD/buttons */
ioport_resource.end = 0x0fffffff;
@@ -139,7 +139,7 @@ void __init plat_mem_setup(void)
/* Read the cobalt id register out of the PCI config space */
PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
- cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
+ cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);
cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);