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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-04-12 18:36:11 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-04-12 18:36:11 -0700 |
| commit | 4505a4938917f4872efcc90bc1e5f4f0ce903b47 (patch) | |
| tree | e049aed70101694b599ae53e6f56bff66d37f8a7 /arch/mips/bcm63xx/cpu.c | |
| parent | fedfb947b2235c1085df97cf52f688b808c3a515 (diff) | |
| parent | f6be75d03c8870be91e6e2a195648ece04b6bb16 (diff) | |
| download | linux-4505a4938917f4872efcc90bc1e5f4f0ce903b47.tar.bz2 | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (36 commits)
MIPS: Calculate proper ebase value for 64-bit kernels
MIPS: Alchemy: DB1200: Remove custom wait implementation
MIPS: Big Sur: Make defconfig more useful.
MIPS: Fix __vmalloc() etc. on MIPS for non-GPL modules
MIPS: Sibyte: Fix M3 TLB exception handler workaround.
MIPS: BCM63xx: Fix build failure in board_bcm963xx.c
MIPS: uasm: Add OR instruction.
MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.
MIPS: BCM63xx: Initialize gpio_out_low & out_high to current value at boot.
MIPS: BCM63xx: Register SSB SPROM fallback in board's first stage callback
MIPS: BCM63xx: Fix typo in cpu-feature-overrides file.
MIPS: BCM63xx: Add support for second uart.
MIPS: BCM63xx: Fix double gpio registration.
MIPS: BCM63xx: Add DWVS0 board
MIPS: BCM63xx: Add the RTA1025W-16 BCM6348-based board to suppported boards.
MIPS: BCM63xx: Fix BCM6338 and BCM6345 gpio count
MIPS: libgcc.h: Checkpatch cleanup
MIPS: Loongson-2F: Flush the branch target history in BTB and RAS
MIPS: Move signal trampolines off of the stack.
MIPS: Preliminary VDSO
...
Diffstat (limited to 'arch/mips/bcm63xx/cpu.c')
| -rw-r--r-- | arch/mips/bcm63xx/cpu.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 70378bb5e3f9..cbb7caf86d77 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -36,6 +36,7 @@ static const unsigned long bcm96338_regs_base[] = { [RSET_TIMER] = BCM_6338_TIMER_BASE, [RSET_WDT] = BCM_6338_WDT_BASE, [RSET_UART0] = BCM_6338_UART0_BASE, + [RSET_UART1] = BCM_6338_UART1_BASE, [RSET_GPIO] = BCM_6338_GPIO_BASE, [RSET_SPI] = BCM_6338_SPI_BASE, [RSET_OHCI0] = BCM_6338_OHCI0_BASE, @@ -72,6 +73,7 @@ static const unsigned long bcm96345_regs_base[] = { [RSET_TIMER] = BCM_6345_TIMER_BASE, [RSET_WDT] = BCM_6345_WDT_BASE, [RSET_UART0] = BCM_6345_UART0_BASE, + [RSET_UART1] = BCM_6345_UART1_BASE, [RSET_GPIO] = BCM_6345_GPIO_BASE, [RSET_SPI] = BCM_6345_SPI_BASE, [RSET_UDC0] = BCM_6345_UDC0_BASE, @@ -109,6 +111,7 @@ static const unsigned long bcm96348_regs_base[] = { [RSET_TIMER] = BCM_6348_TIMER_BASE, [RSET_WDT] = BCM_6348_WDT_BASE, [RSET_UART0] = BCM_6348_UART0_BASE, + [RSET_UART1] = BCM_6348_UART1_BASE, [RSET_GPIO] = BCM_6348_GPIO_BASE, [RSET_SPI] = BCM_6348_SPI_BASE, [RSET_OHCI0] = BCM_6348_OHCI0_BASE, @@ -150,6 +153,7 @@ static const unsigned long bcm96358_regs_base[] = { [RSET_TIMER] = BCM_6358_TIMER_BASE, [RSET_WDT] = BCM_6358_WDT_BASE, [RSET_UART0] = BCM_6358_UART0_BASE, + [RSET_UART1] = BCM_6358_UART1_BASE, [RSET_GPIO] = BCM_6358_GPIO_BASE, [RSET_SPI] = BCM_6358_SPI_BASE, [RSET_OHCI0] = BCM_6358_OHCI0_BASE, @@ -170,6 +174,7 @@ static const unsigned long bcm96358_regs_base[] = { static const int bcm96358_irqs[] = { [IRQ_TIMER] = BCM_6358_TIMER_IRQ, [IRQ_UART0] = BCM_6358_UART0_IRQ, + [IRQ_UART1] = BCM_6358_UART1_IRQ, [IRQ_DSL] = BCM_6358_DSL_IRQ, [IRQ_ENET0] = BCM_6358_ENET0_IRQ, [IRQ_ENET1] = BCM_6358_ENET1_IRQ, |